Lines Matching refs:offset
134 uint64_t value, offset;
157 offset = NXGE_RXDMA_OFFSET(rdc_dmc_offset[i], handle.is_vraddr,
161 offset, rdc_dmc_name[i], value));
335 uint64_t offset;
349 offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_HDL_REG, rdc);
350 NXGE_REG_WR64(handle, offset, page_hdl.value);
492 uint64_t offset;
513 offset = DEF_PT_RDC_REG(portnm);
516 NXGE_REG_WR64(handle, offset, cfg.value);
642 if (RXDMA_RF_BUFF_OFFSET_VALID(rdc_desc_cfg->offset)) {
643 switch (rdc_desc_cfg->offset) {
648 cfg2.bits.ldw.offset = rdc_desc_cfg->offset;
655 cfg2.bits.ldw.offset =
656 rdc_desc_cfg->offset & 0x3;
660 cfg2.bits.ldw.offset = SW_OFFSET_NO_OFFSET;
664 cfg2.bits.ldw.offset = SW_OFFSET_NO_OFFSET;
668 if (RXDMA_BUFF_OFFSET_VALID(rdc_desc_cfg->offset)) {
669 cfg2.bits.ldw.offset = rdc_desc_cfg->offset;
671 cfg2.bits.ldw.offset = SW_OFFSET_NO_OFFSET;
860 uint64_t offset;
871 offset = RDC_RED_RDC_DISC_REG(rdc);
872 NXGE_REG_RD64(handle, offset, &cnt->value);
880 NXGE_REG_WR64(handle, offset, cnt->value);
904 uint64_t offset;
916 offset = RDC_RED_RDC_DISC_REG(rdc);
917 NXGE_REG_RD64(handle, offset, &cnt.value);
925 NXGE_REG_WR64(handle, offset, cnt.value);
1243 uint64_t offset;
1246 offset = RX_DMA_CK_DIV_REG;
1255 NXGE_REG_WR64(handle, offset, clk_div.value);
1263 uint64_t offset;
1266 offset = RED_RAN_INIT_REG;
1271 NXGE_REG_WR64(handle, offset, rand_reg.value);
1280 uint64_t offset;
1283 offset = RED_RAN_INIT_REG;
1285 NXGE_REG_RD64(handle, offset, &rand_reg.value);
1287 NXGE_REG_WR64(handle, offset, rand_reg.value);
1296 uint64_t offset;
1298 offset = RX_ADDR_MD_REG;
1302 NXGE_REG_WR64(handle, offset, md_reg.value);
1310 uint64_t offset;
1312 offset = RX_ADDR_MD_REG;
1315 NXGE_REG_WR64(handle, offset, md_reg.value);
1323 uint64_t offset;
1325 offset = RX_ADDR_MD_REG;
1326 NXGE_REG_RD64(handle, offset, &md_reg.value);
1328 NXGE_REG_WR64(handle, offset, md_reg.value);
1336 uint64_t offset;
1338 offset = RX_ADDR_MD_REG;
1339 NXGE_REG_RD64(handle, offset, &md_reg.value);
1341 NXGE_REG_WR64(handle, offset, md_reg.value);
1352 uint64_t offset;
1363 offset = PT_DRR_WT_REG(portnm);
1366 NXGE_REG_WR64(handle, offset, wt_reg.value);
1376 uint64_t offset;
1387 offset = PT_USE_REG(portnm);
1388 NXGE_REG_RD64(handle, offset, &use_reg.value);
1399 uint64_t offset;
1414 offset = RDC_RED_RDC_PARA_REG(rdc);
1431 NXGE_REG_WR64(handle, offset, wred_reg.value);
1475 uint64_t offset;
1498 offset = REG_RDC_TABLE_OFFSET(table);
1503 NXGE_REG_WR64(handle, offset, rdc_tbl.value);
1504 offset += sizeof (rdc_tbl.value);
1533 uint64_t offset;
1546 offset = REG_RDC_TABLE_OFFSET(table);
1548 NXGE_REG_WR64(handle, offset, tbl_reg.value);
1557 uint64_t offset;
1572 offset = REG_RDC_TABLE_OFFSET(table);
1574 NXGE_REG_RD64(handle, offset, &value);
1577 offset, value));
1578 offset += 8;
1722 uint64_t offset;
1724 offset = RX_CTL_DAT_FIFO_MASK_REG;
1725 NXGE_REG_RD64(handle, offset, &intr_mask.value);
1739 NXGE_REG_WR64(handle, offset, intr_mask.value);
1760 uint64_t offset = RX_CTL_DAT_FIFO_STAT_REG;
1761 NXGE_REG_RD64(handle, offset, &stat->value);