Lines Matching refs:offset
51 * #define NXGE_REG_WR64(handle, offset, val) { \
52 * NXGE_NPI_PIO_WRITE64(handle, (offset), (val)); \
53 * npi_rtrace_update(handle, B_TRUE, &npi_rtracebuf, (uint32_t)offset, \
57 * #define NXGE_REG_WR64(handle, offset, val) {\
58 * NXGE_NPI_PIO_WRITE64(handle, offset, (val));\
59 * rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\
62 * #define NXGE_REG_WR64(handle, offset, val) {\
63 * NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\
70 * #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \
72 * (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset), data))
74 * #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \
76 * (uint64_t *)(NPI_REGP(npi_handle) + offset), data))
130 * offset The offset into the DMA CSR (the register).
149 * offset += ((channel << 1) + 1) << DMA_CSR_SLL;
156 * offset = 0x600070
157 * offset &= 0xff = 0x70
158 * offset += ((3 << 1) + 1) << 9
162 * offset += 0xe00 = 0xe70
171 * channel number by 512 bytes, and get the correct offset to
174 * is offset 512 bytes from the previous channel (count 16 step 512).
176 * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
183 * offset = 0x600070
184 * offset += (3 << 9)
186 * offset += 0x600 = 0x600670
202 uint64_t offset,
207 const char *name = nxge_rx2str((int)offset);
210 offset &= DMA_CSR_MASK;
211 offset += (((channel << 1) + 1) << DMA_CSR_SLL);
213 offset += (channel << DMA_CSR_SLL);
218 (uint64_t *)(handle.regp + (uint32_t)offset), value);
221 (uint64_t *)(handle.regp + offset), value);
226 name, (uint32_t)offset, value);
231 rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, value);