Lines Matching refs:offset
51 * #define NXGE_REG_RD64(handle, offset, val_p) { \
52 * *(val_p) = NXGE_NPI_PIO_READ64(handle, offset); \
53 * npi_rtrace_update(handle, B_FALSE, &npi_rtracebuf, (uint32_t)offset, \
57 * #define NXGE_REG_RD64(handle, offset, val_p) {\
58 * *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
59 * rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, (uint64_t)(*(val_p)));\
62 * #define NXGE_REG_RD64(handle, offset, val_p) {\
66 * *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
74 * n, offset, *val_p);\
78 * cmn_err(CE_WARN, "(FATAL)NXGE_REG_RD64 on offset 0x%x " \
79 * "with -1!!!", offset); \
83 * #define NXGE_REG_RD64(handle, offset, val_p) {\
84 * *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
91 * #define NXGE_NPI_PIO_READ64(npi_handle, offset) \
93 * (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset)))
95 * #define NXGE_NPI_PIO_READ64(npi_handle, offset) \
97 * (uint64_t *)(NPI_REGP(npi_handle) + offset)))
152 * offset The offset into the DMA CSR (the register).
171 * offset += ((channel << 1) + 1) << DMA_CSR_SLL;
178 * offset = 0x600070
179 * offset &= 0xff = 0x70
180 * offset += ((3 << 1) + 1) << 9
184 * offset += 0xe00 = 0xe70
193 * channel number by 512 bytes, and get the correct offset to
196 * is offset 512 bytes from the previous channel (count 16 step 512).
198 * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512
205 * offset = 0x600070
206 * offset += (3 << 9)
208 * offset += 0x600 = 0x600670
224 uint64_t offset,
229 const char *name = nxge_rx2str((int)offset);
232 offset &= DMA_CSR_MASK;
233 offset += (((channel << 1) + 1) << DMA_CSR_SLL);
235 offset += (channel << DMA_CSR_SLL);
240 (uint64_t *)(handle.regp + (uint32_t)offset));
242 *value = ddi_get64(handle.regh, (uint64_t *)(handle.regp + offset));
247 name, (uint32_t)offset, *value);
252 rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, *value);