Lines Matching defs:reg
38 #define XMAC_WAIT_REG(handle, portn, reg, val) {\
42 XMAC_REG_RD(handle, portn, reg, &val);\
47 #define BMAC_WAIT_REG(handle, portn, reg, val) {\
51 BMAC_REG_RD(handle, portn, reg, &val);\
2420 uint32_t reg;
2427 reg = XPCS_CTRL_1_REG;
2430 reg = XPCS_STATUS_1_REG;
2433 reg = XPCS_DEV_ID_REG;
2436 reg = XPCS_SPEED_ABILITY_REG;
2439 reg = XPCS_DEV_IN_PKG_REG;
2442 reg = XPCS_CTRL_2_REG;
2445 reg = XPCS_STATUS_2_REG;
2448 reg = XPCS_PKG_ID_REG;
2451 reg = XPCS_STATUS_REG;
2454 reg = XPCS_TEST_CTRL_REG;
2457 reg = XPCS_CFG_VENDOR_1_REG;
2460 reg = XPCS_DIAG_VENDOR_2_REG;
2463 reg = XPCS_MASK_1_REG;
2466 reg = XPCS_PKT_CNTR_REG;
2469 reg = XPCS_TX_STATE_MC_REG;
2472 reg = XPCS_DESKEW_ERR_CNTR_REG;
2475 reg = XPCS_SYM_ERR_CNTR_L0_L1_REG;
2478 reg = XPCS_SYM_ERR_CNTR_L2_L3_REG;
2481 reg = XPCS_TRAINING_VECTOR_REG;
2490 XPCS_REG_RD(handle, portn, reg, &val);
2500 uint32_t reg;
2507 reg = XPCS_CTRL_1_REG;
2510 reg = XPCS_TEST_CTRL_REG;
2513 reg = XPCS_CFG_VENDOR_1_REG;
2516 reg = XPCS_DIAG_VENDOR_2_REG;
2519 reg = XPCS_MASK_1_REG;
2522 reg = XPCS_PKT_CNTR_REG;
2525 reg = XPCS_DESKEW_ERR_CNTR_REG;
2528 reg = XPCS_TRAINING_VECTOR_REG;
2539 XPCS_REG_WR(handle, portn, reg, val);
3183 "mif mii read port %d reg=0x%x frame=0x%x\n", portn,
3267 "mif mii write port %d reg=0x%x frame=0x%x\n", portn,