Lines Matching defs:MWL_DBG
128 #define MWL_DBG \
131 #define MWL_DBG
356 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_dma_mem(): "
368 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_dma_mem(): "
380 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_dma_mem(): "
386 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_dma_mem(): "
436 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_cmdbuf(): "
471 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_rxring(): "
477 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_rx_ring(): "
486 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_rxring(): "
558 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_tx_ring(): "
564 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_tx_ring(): "
573 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_alloc_tx_ring(): "
693 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_setupdma(): "
735 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_tx_setup(): "
741 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_tx_setup(): "
760 MWL_DBG(MWL_DBG_DMA, "mwl: mwl_setup_txq(): "
802 MWL_DBG(MWL_DBG_FW, "mwl: mwl_loadsym(): "
809 MWL_DBG(MWL_DBG_FW, "mwl: mwl_loadsym(): "
825 MWL_DBG(MWL_DBG_FW, "mwl: mwlFWReset(): "
891 MWL_DBG(MWL_DBG_FW, "mwl: mwlSendBlock(): "
910 MWL_DBG(MWL_DBG_FW, "mwl: mwlSendBlock2(): "
940 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
948 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
956 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
964 MWL_DBG(MWL_DBG_FW, "mwl: mwl_loadfirmware(): "
973 MWL_DBG(MWL_DBG_FW, "mwl: mwl_loadfirmware(): "
984 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
997 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
1019 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
1114 MWL_DBG(MWL_DBG_FW, "mwl: mwl_fwload(): "
1153 MWL_DBG(MWL_DBG_CMD, "mwl: mwlExecuteCmd(): "
1159 MWL_DBG(MWL_DBG_CMD, "mwl: mwlExecuteCmd(): "
1168 MWL_DBG(MWL_DBG_CMD, "mwl: mwlExecuteCmd(): "
1260 MWL_DBG(MWL_DBG_CMD, "mwl: mwl_dumpresult(): "
1264 MWL_DBG(MWL_DBG_CMD, "mwl: mwl_dumpresult(): "
1275 MWL_DBG(MWL_DBG_CMD, "mwl: dumpresult(): "
1278 MWL_DBG(MWL_DBG_CMD, "mwl: dumpresult(): "
1382 MWL_DBG(MWL_DBG_HW, "\n%s:\n", name);
1384 MWL_DBG(MWL_DBG_HW, "[%2d] %3d %3d %3d %3d\n",
1726 MWL_DBG(MWL_DBG_HW, "mwl: mwl_hal_newstation(): "
1866 MWL_DBG(MWL_DBG_HW, "mwl: mwl_hal_settxpower(): "
2231 MWL_DBG(MWL_DBG_MSG, "mwl: mwl_node_alloc(): "
2267 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_alloc(): "
2273 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_alloc(): "
2281 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_alloc(): "
2313 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_delete(): "
2369 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_key_set(): "
2451 MWL_DBG(MWL_DBG_HW, "mwl: mwl_chan_set(): "
2541 MWL_DBG(MWL_DBG_HW, "mwl: mwl_chan2mode(): "
2762 MWL_DBG(MWL_DBG_TX, "mwl: mwl_send(): "
2772 MWL_DBG(MWL_DBG_TX, "mwl: mwl_send():"
2856 MWL_DBG(MWL_DBG_TX, "mwl: mwl_send(): "
2867 MWL_DBG(MWL_DBG_TX, "mwl: mwl_send(): "
2980 MWL_DBG(MWL_DBG_MSG, "mwl: mwl_newstate(): "
2994 MWL_DBG(MWL_DBG_MSG, "mwl: mwl_newstate(): "
3007 MWL_DBG(MWL_DBG_MSG, "mwl: mwl_newstate(): "
3108 MWL_DBG(MWL_DBG_TX, "mwl: mwl_tx_intr(): "
3126 MWL_DBG(MWL_DBG_TX, "mwl: mwl_tx_intr(): "
3193 MWL_DBG(MWL_DBG_CRYPTO, "mwl: mwl_rx_intr(): "
3209 MWL_DBG(MWL_DBG_RX, "mwl: mwl_rx_intr(): "
3217 MWL_DBG(MWL_DBG_RX, "mwl: mwl_rx_intr(): "
3337 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3341 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3345 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3349 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3353 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3357 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3361 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3365 MWL_DBG(MWL_DBG_INTR, "mwl: mwl_intr(): "
3387 MWL_DBG(MWL_DBG_HW, "mwl: mwl_init(): "
3394 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3401 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3408 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3420 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3427 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3435 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3442 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3449 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3470 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3477 MWL_DBG(MWL_DBG_HW, "mwl: init(): "
3493 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3500 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3507 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3516 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3524 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3531 MWL_DBG(MWL_DBG_SR, "mwl: mwl_resume(): "
3551 MWL_DBG(MWL_DBG_HW, "mwl: mwl_stop(): "
3635 MWL_DBG(MWL_DBG_HW, "mwl: mwl_m_start():"
3710 MWL_DBG(MWL_DBG_TX, "mwl: mwl_m_tx(): "
3821 MWL_DBG(MWL_DBG_SR, "mwl: mwl_attach(): "
3829 MWL_DBG(MWL_DBG_SR, "mwl: mwl_attach(): "
3839 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3852 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3866 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3887 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3896 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3901 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3909 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3941 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3946 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3951 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3958 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3968 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3980 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3988 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
3995 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4001 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4012 MWL_DBG(MWL_DBG_ATTACH, "mwl: attach(): "
4074 MWL_DBG(MWL_DBG_ATTACH, "mwl: attach(): "
4084 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4091 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4101 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4108 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4116 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4124 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4131 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4145 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4163 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4176 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4186 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_attach(): "
4247 MWL_DBG(MWL_DBG_SR, "mwl: mwl_detach(): "
4291 MWL_DBG(MWL_DBG_ATTACH, "mwl: mwl_detach(): "