Lines Matching defs:ixgbe
73 static void ixgbe_setup_vmdq_rss_conf(ixgbe_t *ixgbe);
100 static uint32_t ixgbe_get_hw_rx_index(ixgbe_t *ixgbe, uint32_t sw_rx_index);
417 ixgbe_t *ixgbe;
441 ixgbe = kmem_zalloc(sizeof (ixgbe_t), KM_SLEEP);
443 ixgbe->dip = devinfo;
444 ixgbe->instance = instance;
446 hw = &ixgbe->hw;
447 osdep = &ixgbe->osdep;
449 osdep->ixgbe = ixgbe;
452 ddi_set_driver_private(devinfo, ixgbe);
457 ixgbe->fm_capabilities = ixgbe_get_prop(ixgbe, PROP_FM_CAPABLE,
460 ixgbe_fm_init(ixgbe);
461 ixgbe->attach_progress |= ATTACH_PROGRESS_FM_INIT;
467 ixgbe_error(ixgbe, "Failed to map PCI configurations");
470 ixgbe->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
475 if (ixgbe_identify_hardware(ixgbe) != IXGBE_SUCCESS) {
476 ixgbe_error(ixgbe, "Failed to identify hardware");
483 if (ixgbe_regs_map(ixgbe) != IXGBE_SUCCESS) {
484 ixgbe_error(ixgbe, "Failed to map device registers");
487 ixgbe->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
492 ixgbe_init_properties(ixgbe);
493 ixgbe->attach_progress |= ATTACH_PROGRESS_PROPS;
498 if (ixgbe_intr_cb_register(ixgbe) != IXGBE_SUCCESS) {
499 ixgbe_error(ixgbe, "Failed to register interrupt callback");
506 if (ixgbe_alloc_intrs(ixgbe) != IXGBE_SUCCESS) {
507 ixgbe_error(ixgbe, "Failed to allocate interrupts");
510 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
518 if (ixgbe_alloc_rings(ixgbe) != IXGBE_SUCCESS) {
519 ixgbe_error(ixgbe, "Failed to allocate rx and tx rings");
522 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS;
527 if (ixgbe_map_intrs_to_vectors(ixgbe) != IXGBE_SUCCESS) {
528 ixgbe_error(ixgbe, "Failed to map interrupts to vectors");
535 if (ixgbe_add_intr_handlers(ixgbe) != IXGBE_SUCCESS) {
536 ixgbe_error(ixgbe, "Failed to add interrupt handlers");
539 ixgbe->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
544 (void) sprintf(taskqname, "ixgbe%d_sfp_taskq", instance);
545 if ((ixgbe->sfp_taskq = ddi_taskq_create(devinfo, taskqname,
547 ixgbe_error(ixgbe, "sfp_taskq create failed");
550 ixgbe->attach_progress |= ATTACH_PROGRESS_SFP_TASKQ;
555 (void) sprintf(taskqname, "ixgbe%d_overtemp_taskq", instance);
556 if ((ixgbe->overtemp_taskq = ddi_taskq_create(devinfo, taskqname,
558 ixgbe_error(ixgbe, "overtemp_taskq create failed");
561 ixgbe->attach_progress |= ATTACH_PROGRESS_OVERTEMP_TASKQ;
566 (void) sprintf(taskqname, "ixgbe%d_phy_taskq", instance);
567 if ((ixgbe->phy_taskq = ddi_taskq_create(devinfo, taskqname,
569 ixgbe_error(ixgbe, "phy_taskq create failed");
572 ixgbe->attach_progress |= ATTACH_PROGRESS_PHY_TASKQ;
577 if (ixgbe_init_driver_settings(ixgbe) != IXGBE_SUCCESS) {
578 ixgbe_error(ixgbe, "Failed to initialize driver settings");
588 ixgbe_init_locks(ixgbe);
589 ixgbe->attach_progress |= ATTACH_PROGRESS_LOCKS;
594 if (ixgbe_init(ixgbe) != IXGBE_SUCCESS) {
595 ixgbe_error(ixgbe, "Failed to initialize adapter");
598 ixgbe->link_check_complete = B_FALSE;
599 ixgbe->link_check_hrtime = gethrtime() +
601 ixgbe->attach_progress |= ATTACH_PROGRESS_INIT;
603 if (ixgbe_check_acc_handle(ixgbe->osdep.cfg_handle) != DDI_FM_OK) {
604 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
611 ixgbe_init_params(ixgbe);
616 if (ixgbe_init_stats(ixgbe) != IXGBE_SUCCESS) {
617 ixgbe_error(ixgbe, "Failed to initialize statistics");
620 ixgbe->attach_progress |= ATTACH_PROGRESS_STATS;
625 if (ixgbe_register_mac(ixgbe) != IXGBE_SUCCESS) {
626 ixgbe_error(ixgbe, "Failed to register MAC");
629 mac_link_update(ixgbe->mac_hdl, LINK_STATE_UNKNOWN);
630 ixgbe->attach_progress |= ATTACH_PROGRESS_MAC;
632 ixgbe->periodic_id = ddi_periodic_add(ixgbe_link_timer, ixgbe,
634 if (ixgbe->periodic_id == 0) {
635 ixgbe_error(ixgbe, "Failed to add the link check timer");
638 ixgbe->attach_progress |= ATTACH_PROGRESS_LINK_TIMER;
644 if (ixgbe_enable_intrs(ixgbe) != IXGBE_SUCCESS) {
645 ixgbe_error(ixgbe, "Failed to enable DDI interrupts");
648 ixgbe->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
650 ixgbe_log(ixgbe, "%s", ixgbe_ident);
651 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_INITIALIZED);
656 ixgbe_unconfigure(devinfo, ixgbe);
678 ixgbe_t *ixgbe;
697 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
698 if (ixgbe == NULL)
707 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
708 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_STARTED);
709 mutex_enter(&ixgbe->gen_lock);
710 ixgbe_stop(ixgbe, B_TRUE);
711 mutex_exit(&ixgbe->gen_lock);
713 ixgbe_disable_watchdog_timer(ixgbe);
720 if (!ixgbe_rx_drain(ixgbe))
726 ixgbe_unconfigure(devinfo, ixgbe);
744 ixgbe_t *ixgbe;
747 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
749 if (ixgbe == NULL)
752 hw = &ixgbe->hw;
757 ixgbe_disable_adapter_interrupts(ixgbe);
778 ixgbe_unconfigure(dev_info_t *devinfo, ixgbe_t *ixgbe)
783 if (ixgbe->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
784 (void) ixgbe_disable_intrs(ixgbe);
790 if (ixgbe->attach_progress & ATTACH_PROGRESS_LINK_TIMER) {
791 if (ixgbe->periodic_id != NULL) {
792 ddi_periodic_delete(ixgbe->periodic_id);
793 ixgbe->periodic_id = NULL;
800 if (ixgbe->attach_progress & ATTACH_PROGRESS_MAC) {
801 (void) mac_unregister(ixgbe->mac_hdl);
807 if (ixgbe->attach_progress & ATTACH_PROGRESS_STATS) {
808 kstat_delete((kstat_t *)ixgbe->ixgbe_ks);
814 if (ixgbe->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
815 ixgbe_rem_intr_handlers(ixgbe);
821 if (ixgbe->attach_progress & ATTACH_PROGRESS_SFP_TASKQ) {
822 ddi_taskq_destroy(ixgbe->sfp_taskq);
828 if (ixgbe->attach_progress & ATTACH_PROGRESS_OVERTEMP_TASKQ) {
829 ddi_taskq_destroy(ixgbe->overtemp_taskq);
835 if (ixgbe->attach_progress & ATTACH_PROGRESS_PHY_TASKQ) {
836 ddi_taskq_destroy(ixgbe->phy_taskq);
842 if (ixgbe->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) {
843 ixgbe_rem_intrs(ixgbe);
849 (void) ddi_cb_unregister(ixgbe->cb_hdl);
854 if (ixgbe->attach_progress & ATTACH_PROGRESS_PROPS) {
861 if (ixgbe->attach_progress & ATTACH_PROGRESS_INIT) {
862 mutex_enter(&ixgbe->gen_lock);
863 ixgbe_chip_stop(ixgbe);
864 mutex_exit(&ixgbe->gen_lock);
870 if (ixgbe->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
871 if (ixgbe->osdep.reg_handle != NULL)
872 ddi_regs_map_free(&ixgbe->osdep.reg_handle);
878 if (ixgbe->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
879 if (ixgbe->osdep.cfg_handle != NULL)
880 pci_config_teardown(&ixgbe->osdep.cfg_handle);
886 if (ixgbe->attach_progress & ATTACH_PROGRESS_LOCKS) {
887 ixgbe_destroy_locks(ixgbe);
893 if (ixgbe->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) {
894 ixgbe_free_rings(ixgbe);
900 if (ixgbe->attach_progress & ATTACH_PROGRESS_FM_INIT) {
901 ixgbe_fm_fini(ixgbe);
907 kmem_free(ixgbe, sizeof (ixgbe_t));
917 ixgbe_register_mac(ixgbe_t *ixgbe)
919 struct ixgbe_hw *hw = &ixgbe->hw;
927 mac->m_driver = ixgbe;
928 mac->m_dip = ixgbe->dip;
932 mac->m_max_sdu = ixgbe->default_mtu;
937 status = mac_register(mac, &ixgbe->mac_hdl);
948 ixgbe_identify_hardware(ixgbe_t *ixgbe)
950 struct ixgbe_hw *hw = &ixgbe->hw;
951 struct ixgbe_osdep *osdep = &ixgbe->osdep;
979 IXGBE_DEBUGLOG_0(ixgbe, "identify 82598 adapter\n");
980 ixgbe->capab = &ixgbe_82598eb_cap;
983 ixgbe->capab->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
984 ixgbe->capab->other_intr |= IXGBE_EICR_GPI_SDP1;
985 ixgbe->capab->other_gpie |= IXGBE_SDP1_GPIEN;
990 IXGBE_DEBUGLOG_0(ixgbe, "identify 82599 adapter\n");
991 ixgbe->capab = &ixgbe_82599eb_cap;
994 ixgbe->capab->flags |= IXGBE_FLAG_TEMP_SENSOR_CAPABLE;
995 ixgbe->capab->other_intr |= IXGBE_EICR_GPI_SDP0;
996 ixgbe->capab->other_gpie |= IXGBE_SDP0_GPIEN;
1001 IXGBE_DEBUGLOG_0(ixgbe, "identify X540 adapter\n");
1002 ixgbe->capab = &ixgbe_X540_cap;
1011 IXGBE_DEBUGLOG_0(ixgbe, "identify X550 adapter\n");
1012 ixgbe->capab = &ixgbe_X550_cap;
1015 ixgbe->capab->flags |= IXGBE_FLAG_SFP_PLUG_CAPABLE;
1022 ixgbe->capab->other_intr |=
1024 ixgbe->capab->other_gpie |= IXGBE_SDP0_GPIEN_X540;
1029 IXGBE_DEBUGLOG_1(ixgbe,
1043 ixgbe_regs_map(ixgbe_t *ixgbe)
1045 dev_info_t *devinfo = ixgbe->dip;
1046 struct ixgbe_hw *hw = &ixgbe->hw;
1047 struct ixgbe_osdep *osdep = &ixgbe->osdep;
1075 ixgbe_init_properties(ixgbe_t *ixgbe)
1081 ixgbe_get_conf(ixgbe);
1092 ixgbe_init_driver_settings(ixgbe_t *ixgbe)
1094 struct ixgbe_hw *hw = &ixgbe->hw;
1095 dev_info_t *devinfo = ixgbe->dip;
1114 ixgbe->sys_page_size = ddi_ptob(devinfo, (ulong_t)1);
1123 rx_size = ixgbe->max_frame_size + IPHDR_ALIGN_ROOM;
1124 ixgbe->rx_buf_size = ((rx_size >> 10) +
1130 tx_size = ixgbe->max_frame_size;
1131 ixgbe->tx_buf_size = ((tx_size >> 10) +
1137 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
1138 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1139 rx_ring = &ixgbe->rx_rings[i];
1141 rx_ring->ixgbe = ixgbe;
1143 rx_ring->hw_index = ixgbe_get_hw_rx_index(ixgbe, i);
1146 for (i = 0; i < ixgbe->num_rx_groups; i++) {
1147 rx_group = &ixgbe->rx_groups[i];
1149 rx_group->ixgbe = ixgbe;
1152 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1153 tx_ring = &ixgbe->tx_rings[i];
1155 tx_ring->ixgbe = ixgbe;
1156 if (ixgbe->tx_head_wb_enable)
1161 tx_ring->ring_size = ixgbe->tx_ring_size;
1162 tx_ring->free_list_size = ixgbe->tx_ring_size +
1163 (ixgbe->tx_ring_size >> 1);
1170 ixgbe->intr_throttling[i] = ixgbe->intr_throttling[0];
1175 ixgbe->link_state = LINK_STATE_UNKNOWN;
1184 ixgbe_init_locks(ixgbe_t *ixgbe)
1190 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1191 rx_ring = &ixgbe->rx_rings[i];
1193 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1196 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1197 tx_ring = &ixgbe->tx_rings[i];
1199 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1201 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1203 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1205 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1208 mutex_init(&ixgbe->gen_lock, NULL,
1209 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1211 mutex_init(&ixgbe->watchdog_lock, NULL,
1212 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1219 ixgbe_destroy_locks(ixgbe_t *ixgbe)
1225 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1226 rx_ring = &ixgbe->rx_rings[i];
1230 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1231 tx_ring = &ixgbe->tx_rings[i];
1238 mutex_destroy(&ixgbe->gen_lock);
1239 mutex_destroy(&ixgbe->watchdog_lock);
1245 ixgbe_t *ixgbe;
1248 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
1249 if (ixgbe == NULL)
1252 mutex_enter(&ixgbe->gen_lock);
1254 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
1255 if (ixgbe_start(ixgbe, B_FALSE) != IXGBE_SUCCESS) {
1256 mutex_exit(&ixgbe->gen_lock);
1263 ixgbe_enable_watchdog_timer(ixgbe);
1266 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_SUSPENDED);
1268 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
1269 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1270 mac_tx_ring_update(ixgbe->mac_hdl,
1271 ixgbe->tx_rings[i].ring_handle);
1275 mutex_exit(&ixgbe->gen_lock);
1283 ixgbe_t *ixgbe;
1285 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
1286 if (ixgbe == NULL)
1289 mutex_enter(&ixgbe->gen_lock);
1291 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_SUSPENDED);
1292 if (!(ixgbe->ixgbe_state & IXGBE_STARTED)) {
1293 mutex_exit(&ixgbe->gen_lock);
1296 ixgbe_stop(ixgbe, B_FALSE);
1298 mutex_exit(&ixgbe->gen_lock);
1303 ixgbe_disable_watchdog_timer(ixgbe);
1312 ixgbe_init(ixgbe_t *ixgbe)
1314 struct ixgbe_hw *hw = &ixgbe->hw;
1318 mutex_enter(&ixgbe->gen_lock);
1337 ixgbe_error(ixgbe,
1343 ixgbe_error(ixgbe,
1349 ixgbe_error(ixgbe,
1353 "allow_unsupported_sfp=1 in ixgbe.conf.");
1356 ixgbe_error(ixgbe,
1359 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1368 ixgbe_error(ixgbe,
1370 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1384 ixgbe_error(ixgbe,
1387 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1394 * & flow control type is controlled by ixgbe.conf
1409 (void) ixgbe_driver_setup_link(ixgbe, B_FALSE);
1414 if (ixgbe_chip_start(ixgbe) != IXGBE_SUCCESS) {
1415 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1425 (void) ddi_prop_update_string(DDI_DEV_T_NONE, ixgbe->dip,
1429 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
1433 mutex_exit(&ixgbe->gen_lock);
1442 mutex_exit(&ixgbe->gen_lock);
1443 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1451 ixgbe_chip_start(ixgbe_t *ixgbe)
1453 struct ixgbe_hw *hw = &ixgbe->hw;
1456 ASSERT(mutex_owned(&ixgbe->gen_lock));
1462 if (!ixgbe_find_mac_address(ixgbe)) {
1463 ixgbe_error(ixgbe, "Failed to get the mac address");
1472 ixgbe_error(ixgbe, "Invalid mac address");
1480 if (ixgbe->relax_order_enable == B_TRUE)
1486 ixgbe_setup_adapter_vector(ixgbe);
1491 ixgbe_init_unicst(ixgbe);
1496 ixgbe_setup_multicst(ixgbe);
1501 for (i = 0; i < ixgbe->intr_cnt; i++) {
1502 IXGBE_WRITE_REG(hw, IXGBE_EITR(i), ixgbe->intr_throttling[i]);
1515 * Currently, the only known adapter which supports EEE in the ixgbe
1534 ixgbe_get_hw_state(ixgbe);
1548 ixgbe_chip_stop(ixgbe_t *ixgbe)
1550 struct ixgbe_hw *hw = &ixgbe->hw;
1553 ASSERT(mutex_owned(&ixgbe->gen_lock));
1579 ixgbe_error(ixgbe, "Error while entering LPLU: %d", rv);
1605 ixgbe_reset(ixgbe_t *ixgbe)
1612 ixgbe_disable_watchdog_timer(ixgbe);
1614 mutex_enter(&ixgbe->gen_lock);
1616 ASSERT(ixgbe->ixgbe_state & IXGBE_STARTED);
1617 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_STARTED);
1619 ixgbe_stop(ixgbe, B_FALSE);
1621 if (ixgbe_start(ixgbe, B_FALSE) != IXGBE_SUCCESS) {
1622 mutex_exit(&ixgbe->gen_lock);
1629 ixgbe->link_check_complete = B_FALSE;
1630 ixgbe->link_check_hrtime = gethrtime() +
1633 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_STARTED);
1635 if (!(ixgbe->ixgbe_state & IXGBE_SUSPENDED)) {
1636 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1637 mac_tx_ring_update(ixgbe->mac_hdl,
1638 ixgbe->tx_rings[i].ring_handle);
1642 mutex_exit(&ixgbe->gen_lock);
1647 ixgbe_enable_watchdog_timer(ixgbe);
1656 ixgbe_tx_clean(ixgbe_t *ixgbe)
1666 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1667 tx_ring = &ixgbe->tx_rings[i];
1702 if (ixgbe->tx_head_wb_enable)
1705 IXGBE_WRITE_REG(&ixgbe->hw,
1707 IXGBE_WRITE_REG(&ixgbe->hw,
1726 ixgbe_tx_drain(ixgbe_t *ixgbe)
1745 for (j = 0; j < ixgbe->num_tx_rings; j++) {
1746 tx_ring = &ixgbe->tx_rings[j];
1764 ixgbe_rx_drain(ixgbe_t *ixgbe)
1780 done = (ixgbe->rcb_pending == 0);
1795 ixgbe_start(ixgbe_t *ixgbe, boolean_t alloc_buffer)
1797 struct ixgbe_hw *hw = &ixgbe->hw;
1800 ASSERT(mutex_owned(&ixgbe->gen_lock));
1803 if (ixgbe_alloc_rx_data(ixgbe) != IXGBE_SUCCESS) {
1804 ixgbe_error(ixgbe,
1810 if (ixgbe_alloc_dma(ixgbe) != IXGBE_SUCCESS) {
1811 ixgbe_error(ixgbe, "Failed to allocate DMA resource");
1815 ixgbe->tx_ring_init = B_TRUE;
1817 ixgbe->tx_ring_init = B_FALSE;
1820 for (i = 0; i < ixgbe->num_rx_rings; i++)
1821 mutex_enter(&ixgbe->rx_rings[i].rx_lock);
1822 for (i = 0; i < ixgbe->num_tx_rings; i++)
1823 mutex_enter(&ixgbe->tx_rings[i].tx_lock);
1828 if (ixgbe_chip_start(ixgbe) != IXGBE_SUCCESS) {
1829 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1847 (void) ixgbe_driver_setup_link(ixgbe, B_TRUE);
1848 ixgbe_get_hw_state(ixgbe);
1851 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
1858 ixgbe_setup_rings(ixgbe);
1865 atomic_and_32(&ixgbe->ixgbe_state, ~(IXGBE_ERROR
1872 ixgbe_enable_adapter_interrupts(ixgbe);
1874 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--)
1875 mutex_exit(&ixgbe->tx_rings[i].tx_lock);
1876 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--)
1877 mutex_exit(&ixgbe->rx_rings[i].rx_lock);
1882 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--)
1883 mutex_exit(&ixgbe->tx_rings[i].tx_lock);
1884 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--)
1885 mutex_exit(&ixgbe->rx_rings[i].rx_lock);
1887 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1896 ixgbe_stop(ixgbe_t *ixgbe, boolean_t free_buffer)
1900 ASSERT(mutex_owned(&ixgbe->gen_lock));
1905 ixgbe_disable_adapter_interrupts(ixgbe);
1910 (void) ixgbe_tx_drain(ixgbe);
1912 for (i = 0; i < ixgbe->num_rx_rings; i++)
1913 mutex_enter(&ixgbe->rx_rings[i].rx_lock);
1914 for (i = 0; i < ixgbe->num_tx_rings; i++)
1915 mutex_enter(&ixgbe->tx_rings[i].tx_lock);
1920 ixgbe_chip_stop(ixgbe);
1922 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
1923 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1929 ixgbe_tx_clean(ixgbe);
1931 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--)
1932 mutex_exit(&ixgbe->tx_rings[i].tx_lock);
1933 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--)
1934 mutex_exit(&ixgbe->rx_rings[i].rx_lock);
1936 if (ixgbe->link_state == LINK_STATE_UP) {
1937 ixgbe->link_state = LINK_STATE_UNKNOWN;
1938 mac_link_update(ixgbe->mac_hdl, ixgbe->link_state);
1945 ixgbe_free_dma(ixgbe);
1946 ixgbe_free_rx_data(ixgbe);
1958 ixgbe_t *ixgbe = (ixgbe_t *)arg1;
1966 ASSERT(ixgbe->intr_type == DDI_INTR_TYPE_MSIX);
1968 int, ixgbe->intr_cnt);
1969 if (ixgbe_intr_adjust(ixgbe, cbaction, count) !=
1971 ixgbe_error(ixgbe,
1977 IXGBE_DEBUGLOG_1(ixgbe, "DDI CB: action 0x%x NOT supported",
1990 ixgbe_intr_adjust(ixgbe_t *ixgbe, ddi_cb_action_t cbaction, int count)
1998 ixgbe->intr_cnt + count > ixgbe->intr_cnt_max) ||
2000 ixgbe->intr_cnt - count < ixgbe->intr_cnt_min))
2003 if (!(ixgbe->ixgbe_state & IXGBE_STARTED)) {
2007 for (i = 0; i < ixgbe->num_rx_rings; i++)
2008 mac_ring_intr_set(ixgbe->rx_rings[i].ring_handle, NULL);
2009 for (i = 0; i < ixgbe->num_tx_rings; i++)
2010 mac_ring_intr_set(ixgbe->tx_rings[i].ring_handle, NULL);
2012 mutex_enter(&ixgbe->gen_lock);
2013 ixgbe->ixgbe_state &= ~IXGBE_STARTED;
2014 ixgbe->ixgbe_state |= IXGBE_INTR_ADJUST;
2015 ixgbe->ixgbe_state |= IXGBE_SUSPENDED;
2016 mac_link_update(ixgbe->mac_hdl, LINK_STATE_UNKNOWN);
2018 ixgbe_stop(ixgbe, B_FALSE);
2022 if (ixgbe->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
2023 rc = ixgbe_disable_intrs(ixgbe);
2026 ixgbe->attach_progress &= ~ATTACH_PROGRESS_ENABLE_INTR;
2031 if (ixgbe->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
2032 ixgbe_rem_intr_handlers(ixgbe);
2034 ixgbe->attach_progress &= ~ATTACH_PROGRESS_ADD_INTR;
2039 bzero(&ixgbe->vect_map, sizeof (ixgbe->vect_map));
2042 rc = ddi_intr_alloc(ixgbe->dip, ixgbe->htable,
2043 DDI_INTR_TYPE_MSIX, ixgbe->intr_cnt, count, &actual,
2046 ixgbe_log(ixgbe, "Adjust interrupts failed."
2051 ixgbe->intr_cnt += count;
2055 for (i = ixgbe->intr_cnt - count;
2056 i < ixgbe->intr_cnt; i ++) {
2057 rc = ddi_intr_free(ixgbe->htable[i]);
2058 ixgbe->htable[i] = NULL;
2060 ixgbe_log(ixgbe, "Adjust interrupts failed."
2066 ixgbe->intr_cnt -= count;
2073 rc = ddi_intr_get_pri(ixgbe->htable[0], &ixgbe->intr_pri);
2075 ixgbe_log(ixgbe,
2079 rc = ddi_intr_get_cap(ixgbe->htable[0], &ixgbe->intr_cap);
2081 ixgbe_log(ixgbe, "Get interrupt cap failed: %d", rc);
2084 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
2089 if (ixgbe_map_intrs_to_vectors(ixgbe) != IXGBE_SUCCESS) {
2090 ixgbe_error(ixgbe,
2098 if (ixgbe_add_intr_handlers(ixgbe) != IXGBE_SUCCESS) {
2099 ixgbe_error(ixgbe, "IRM CB: Failed to add interrupt handlers");
2102 ixgbe->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
2108 if (ixgbe_enable_intrs(ixgbe) != IXGBE_SUCCESS) {
2109 ixgbe_error(ixgbe, "IRM CB: Failed to enable DDI interrupts");
2112 ixgbe->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
2113 if (ixgbe_start(ixgbe, B_FALSE) != IXGBE_SUCCESS) {
2114 ixgbe_error(ixgbe, "IRM CB: Failed to start");
2117 ixgbe->ixgbe_state &= ~IXGBE_INTR_ADJUST;
2118 ixgbe->ixgbe_state &= ~IXGBE_SUSPENDED;
2119 ixgbe->ixgbe_state |= IXGBE_STARTED;
2120 mutex_exit(&ixgbe->gen_lock);
2122 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2123 mac_ring_intr_set(ixgbe->rx_rings[i].ring_handle,
2124 ixgbe->htable[ixgbe->rx_rings[i].intr_vector]);
2126 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2127 mac_ring_intr_set(ixgbe->tx_rings[i].ring_handle,
2128 ixgbe->htable[ixgbe->tx_rings[i].intr_vector]);
2132 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2133 mac_tx_ring_update(ixgbe->mac_hdl,
2134 ixgbe->tx_rings[i].ring_handle);
2137 IXGBE_DEBUGLOG_3(ixgbe,
2139 ixgbe->intr_cnt, ixgbe->intr_cnt_min, ixgbe->intr_cnt_max);
2143 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
2144 mutex_exit(&ixgbe->gen_lock);
2152 ixgbe_intr_cb_register(ixgbe_t *ixgbe)
2154 if (ddi_cb_register(ixgbe->dip, DDI_CB_FLAG_INTR, ixgbe_cbfunc,
2155 ixgbe, NULL, &ixgbe->cb_hdl) != DDI_SUCCESS) {
2158 IXGBE_DEBUGLOG_0(ixgbe, "Interrupt callback function registered.");
2166 ixgbe_alloc_rings(ixgbe_t *ixgbe)
2171 ixgbe->rx_rings = kmem_zalloc(
2172 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings,
2175 if (ixgbe->rx_rings == NULL) {
2182 ixgbe->tx_rings = kmem_zalloc(
2183 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings,
2186 if (ixgbe->tx_rings == NULL) {
2187 kmem_free(ixgbe->rx_rings,
2188 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings);
2189 ixgbe->rx_rings = NULL;
2196 ixgbe->rx_groups = kmem_zalloc(
2197 sizeof (ixgbe_rx_group_t) * ixgbe->num_rx_groups,
2200 if (ixgbe->rx_groups == NULL) {
2201 kmem_free(ixgbe->rx_rings,
2202 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings);
2203 kmem_free(ixgbe->tx_rings,
2204 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings);
2205 ixgbe->rx_rings = NULL;
2206 ixgbe->tx_rings = NULL;
2217 ixgbe_free_rings(ixgbe_t *ixgbe)
2219 if (ixgbe->rx_rings != NULL) {
2220 kmem_free(ixgbe->rx_rings,
2221 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings);
2222 ixgbe->rx_rings = NULL;
2225 if (ixgbe->tx_rings != NULL) {
2226 kmem_free(ixgbe->tx_rings,
2227 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings);
2228 ixgbe->tx_rings = NULL;
2231 if (ixgbe->rx_groups != NULL) {
2232 kmem_free(ixgbe->rx_groups,
2233 sizeof (ixgbe_rx_group_t) * ixgbe->num_rx_groups);
2234 ixgbe->rx_groups = NULL;
2239 ixgbe_alloc_rx_data(ixgbe_t *ixgbe)
2244 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2245 rx_ring = &ixgbe->rx_rings[i];
2252 ixgbe_free_rx_data(ixgbe);
2257 ixgbe_free_rx_data(ixgbe_t *ixgbe)
2263 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2264 rx_ring = &ixgbe->rx_rings[i];
2266 mutex_enter(&ixgbe->rx_pending_lock);
2278 mutex_exit(&ixgbe->rx_pending_lock);
2286 ixgbe_setup_rings(ixgbe_t *ixgbe)
2295 ixgbe_setup_rx(ixgbe);
2297 ixgbe_setup_tx(ixgbe);
2303 ixgbe_t *ixgbe = rx_ring->ixgbe;
2305 struct ixgbe_hw *hw = &ixgbe->hw;
2315 ASSERT(mutex_owned(&ixgbe->gen_lock));
2317 for (i = 0; i < ixgbe->rx_ring_size; i++) {
2377 reg_val = (ixgbe->rx_buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) |
2384 ixgbe_setup_rx(ixgbe_t *ixgbe)
2387 struct ixgbe_hw *hw = &ixgbe->hw;
2400 if (ixgbe->classify_mode != IXGBE_CLASSIFY_VMDQ &&
2401 ixgbe->classify_mode != IXGBE_CLASSIFY_VMDQ_RSS) {
2408 if (ixgbe->num_rx_groups > 32) {
2413 for (i = 0; i < ixgbe->capab->max_rx_grp_num; i++) {
2438 if (ixgbe->rx_hcksum_enable) {
2447 switch (ixgbe->classify_mode) {
2453 ixgbe_setup_rss(ixgbe);
2461 ixgbe_setup_vmdq(ixgbe);
2469 ixgbe_setup_vmdq_rss(ixgbe);
2490 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2491 rx_ring = &ixgbe->rx_rings[i];
2499 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2500 index = ixgbe->rx_rings[i].hw_index;
2514 reg_val |= (ixgbe->default_mtu + sizeof (struct ether_header)
2522 if (ixgbe->default_mtu > ETHERMTU)
2531 if (ixgbe->lro_enable) {
2532 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2540 if (ixgbe->rx_buf_size == IXGBE_PKG_BUF_16k)
2563 ixgbe_t *ixgbe = tx_ring->ixgbe;
2564 struct ixgbe_hw *hw = &ixgbe->hw;
2571 ASSERT(mutex_owned(&ixgbe->gen_lock));
2596 if (ixgbe->tx_head_wb_enable) {
2640 if (ixgbe->tx_ring_init == B_TRUE) {
2653 ixgbe_setup_tx(ixgbe_t *ixgbe)
2655 struct ixgbe_hw *hw = &ixgbe->hw;
2661 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2662 tx_ring = &ixgbe->tx_rings[i];
2670 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2744 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2745 tx_ring = &ixgbe->tx_rings[i];
2756 ixgbe_setup_rss(ixgbe_t *ixgbe)
2758 struct ixgbe_hw *hw = &ixgbe->hw;
2764 ixgbe_setup_rss_table(ixgbe);
2786 ixgbe_setup_vmdq(ixgbe_t *ixgbe)
2788 struct ixgbe_hw *hw = &ixgbe->hw;
2843 ixgbe_setup_vmdq_rss(ixgbe_t *ixgbe)
2845 struct ixgbe_hw *hw = &ixgbe->hw;
2852 ixgbe_setup_rss_table(ixgbe);
2903 if (ixgbe->num_rx_groups > 32) {
2944 ixgbe_setup_rss_table(ixgbe_t *ixgbe)
2946 struct ixgbe_hw *hw = &ixgbe->hw;
2965 switch (ixgbe->hw.mac.type) {
2986 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
3037 ixgbe_init_unicst(ixgbe_t *ixgbe)
3039 struct ixgbe_hw *hw = &ixgbe->hw;
3052 if (!ixgbe->unicst_init) {
3056 ixgbe->unicst_total = hw->mac.num_rar_entries;
3057 ixgbe->unicst_avail = ixgbe->unicst_total;
3058 for (slot = 0; slot < ixgbe->unicst_total; slot++) {
3059 mac_addr = ixgbe->unicst_addr[slot].mac.addr;
3062 ixgbe->unicst_addr[slot].mac.set = 0;
3064 ixgbe->unicst_init = B_TRUE;
3067 for (slot = 0; slot < ixgbe->unicst_total; slot++) {
3068 mac_addr = ixgbe->unicst_addr[slot].mac.addr;
3069 if (ixgbe->unicst_addr[slot].mac.set == 1) {
3071 ixgbe->unicst_addr[slot].mac.group_index,
3086 ixgbe_unicst_find(ixgbe_t *ixgbe, const uint8_t *mac_addr)
3090 ASSERT(mutex_owned(&ixgbe->gen_lock));
3092 for (slot = 0; slot < ixgbe->unicst_total; slot++) {
3093 if (bcmp(ixgbe->unicst_addr[slot].mac.addr,
3105 ixgbe_multicst_add(ixgbe_t *ixgbe, const uint8_t *multiaddr)
3107 ASSERT(mutex_owned(&ixgbe->gen_lock));
3113 if (ixgbe->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) {
3118 &ixgbe->mcast_table[ixgbe->mcast_count], ETHERADDRL);
3119 ixgbe->mcast_count++;
3124 ixgbe_setup_multicst(ixgbe);
3126 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
3127 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
3138 ixgbe_multicst_remove(ixgbe_t *ixgbe, const uint8_t *multiaddr)
3142 ASSERT(mutex_owned(&ixgbe->gen_lock));
3144 for (i = 0; i < ixgbe->mcast_count; i++) {
3145 if (bcmp(multiaddr, &ixgbe->mcast_table[i],
3147 for (i++; i < ixgbe->mcast_count; i++) {
3148 ixgbe->mcast_table[i - 1] =
3149 ixgbe->mcast_table[i];
3151 ixgbe->mcast_count--;
3159 ixgbe_setup_multicst(ixgbe);
3161 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
3162 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
3176 ixgbe_setup_multicst(ixgbe_t *ixgbe)
3180 struct ixgbe_hw *hw = &ixgbe->hw;
3182 ASSERT(mutex_owned(&ixgbe->gen_lock));
3184 ASSERT(ixgbe->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES);
3186 mc_addr_list = (uint8_t *)ixgbe->mcast_table;
3187 mc_addr_count = ixgbe->mcast_count;
3203 ixgbe_setup_vmdq_rss_conf(ixgbe_t *ixgbe)
3205 struct ixgbe_hw *hw = &ixgbe->hw;
3218 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
3219 if (ixgbe->num_rx_groups > 4) {
3220 ixgbe->num_rx_rings = ixgbe->num_rx_groups;
3222 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
3243 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
3244 if (ixgbe->num_rx_groups == 1) {
3245 ixgbe->num_rx_rings = min(8, ring_per_group);
3246 } else if (ixgbe->num_rx_groups <= 32) {
3247 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
3249 } else if (ixgbe->num_rx_groups <= 64) {
3250 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
3259 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
3261 if (ixgbe->num_rx_groups == 1 && ring_per_group == 1) {
3262 ixgbe->classify_mode = IXGBE_CLASSIFY_NONE;
3263 } else if (ixgbe->num_rx_groups != 1 && ring_per_group == 1) {
3264 ixgbe->classify_mode = IXGBE_CLASSIFY_VMDQ;
3265 } else if (ixgbe->num_rx_groups != 1 && ring_per_group != 1) {
3266 ixgbe->classify_mode = IXGBE_CLASSIFY_VMDQ_RSS;
3268 ixgbe->classify_mode = IXGBE_CLASSIFY_RSS;
3271 IXGBE_DEBUGLOG_2(ixgbe, "rx group number:%d, rx ring number:%d",
3272 ixgbe->num_rx_groups, ixgbe->num_rx_rings);
3279 * file ixgbe.conf.
3288 ixgbe_get_conf(ixgbe_t *ixgbe)
3290 struct ixgbe_hw *hw = &ixgbe->hw;
3294 * ixgbe driver supports the following user configurations:
3317 ixgbe->default_mtu = ixgbe_get_prop(ixgbe, PROP_DEFAULT_MTU,
3318 MIN_MTU, ixgbe->capab->max_mtu, DEFAULT_MTU);
3320 ixgbe->max_frame_size = ixgbe->default_mtu +
3326 flow_control = ixgbe_get_prop(ixgbe, PROP_FLOW_CONTROL,
3340 ixgbe->num_tx_rings = ixgbe_get_prop(ixgbe, PROP_TX_QUEUE_NUM,
3341 ixgbe->capab->min_tx_que_num,
3342 ixgbe->capab->max_tx_que_num,
3343 ixgbe->capab->def_tx_que_num);
3344 ixgbe->tx_ring_size = ixgbe_get_prop(ixgbe, PROP_TX_RING_SIZE,
3347 ixgbe->num_rx_rings = ixgbe_get_prop(ixgbe, PROP_RX_QUEUE_NUM,
3348 ixgbe->capab->min_rx_que_num,
3349 ixgbe->capab->max_rx_que_num,
3350 ixgbe->capab->def_rx_que_num);
3351 ixgbe->rx_ring_size = ixgbe_get_prop(ixgbe, PROP_RX_RING_SIZE,
3357 ixgbe->num_rx_groups = ixgbe_get_prop(ixgbe, PROP_RX_GROUP_NUM,
3358 ixgbe->capab->min_rx_grp_num, ixgbe->capab->max_rx_grp_num,
3359 ixgbe->capab->def_rx_grp_num);
3361 ixgbe->mr_enable = ixgbe_get_prop(ixgbe, PROP_MR_ENABLE,
3364 if (ixgbe->mr_enable == B_FALSE) {
3365 ixgbe->num_tx_rings = 1;
3366 ixgbe->num_rx_rings = 1;
3367 ixgbe->num_rx_groups = 1;
3368 ixgbe->classify_mode = IXGBE_CLASSIFY_NONE;
3370 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
3371 max(ixgbe->num_rx_rings / ixgbe->num_rx_groups, 1);
3377 ixgbe_setup_vmdq_rss_conf(ixgbe);
3388 ixgbe->intr_force = ixgbe_get_prop(ixgbe, PROP_INTR_FORCE,
3391 ixgbe->tx_hcksum_enable = ixgbe_get_prop(ixgbe, PROP_TX_HCKSUM_ENABLE,
3393 ixgbe->rx_hcksum_enable = ixgbe_get_prop(ixgbe, PROP_RX_HCKSUM_ENABLE,
3395 ixgbe->lso_enable = ixgbe_get_prop(ixgbe, PROP_LSO_ENABLE,
3397 ixgbe->lro_enable = ixgbe_get_prop(ixgbe, PROP_LRO_ENABLE,
3399 ixgbe->tx_head_wb_enable = ixgbe_get_prop(ixgbe, PROP_TX_HEAD_WB_ENABLE,
3401 ixgbe->relax_order_enable = ixgbe_get_prop(ixgbe,
3409 ixgbe->tx_head_wb_enable = B_FALSE;
3413 * ixgbe LSO needs the tx h/w checksum support.
3417 if (ixgbe->tx_hcksum_enable == B_FALSE) {
3418 ixgbe->lso_enable = B_FALSE;
3422 * ixgbe LRO needs the rx h/w checksum support.
3426 if (ixgbe->rx_hcksum_enable == B_FALSE) {
3427 ixgbe->lro_enable = B_FALSE;
3431 * ixgbe LRO only supported by 82599, X540 and X550
3434 ixgbe->lro_enable = B_FALSE;
3436 ixgbe->tx_copy_thresh = ixgbe_get_prop(ixgbe, PROP_TX_COPY_THRESHOLD,
3439 ixgbe->tx_recycle_thresh = ixgbe_get_prop(ixgbe,
3442 ixgbe->tx_overload_thresh = ixgbe_get_prop(ixgbe,
3445 ixgbe->tx_resched_thresh = ixgbe_get_prop(ixgbe,
3449 ixgbe->rx_copy_thresh = ixgbe_get_prop(ixgbe, PROP_RX_COPY_THRESHOLD,
3452 ixgbe->rx_limit_per_intr = ixgbe_get_prop(ixgbe, PROP_RX_LIMIT_PER_INTR,
3456 ixgbe->intr_throttling[0] = ixgbe_get_prop(ixgbe, PROP_INTR_THROTTLING,
3457 ixgbe->capab->min_intr_throttle,
3458 ixgbe->capab->max_intr_throttle,
3459 ixgbe->capab->def_intr_throttle);
3468 ixgbe->intr_throttling[0] = ixgbe->intr_throttling[0] & 0xFF8;
3470 hw->allow_unsupported_sfp = ixgbe_get_prop(ixgbe,
3475 ixgbe_init_params(ixgbe_t *ixgbe)
3477 struct ixgbe_hw *hw = &ixgbe->hw;
3508 ixgbe->speeds_supported = speeds_supported;
3514 ixgbe->param_en_10000fdx_cap = 1;
3515 ixgbe->param_adv_10000fdx_cap = 1;
3517 ixgbe->param_en_10000fdx_cap = 0;
3518 ixgbe->param_adv_10000fdx_cap = 0;
3522 ixgbe->param_en_5000fdx_cap = 1;
3523 ixgbe->param_adv_5000fdx_cap = 1;
3525 ixgbe->param_en_5000fdx_cap = 0;
3526 ixgbe->param_adv_5000fdx_cap = 0;
3530 ixgbe->param_en_2500fdx_cap = 1;
3531 ixgbe->param_adv_2500fdx_cap = 1;
3533 ixgbe->param_en_2500fdx_cap = 0;
3534 ixgbe->param_adv_2500fdx_cap = 0;
3538 ixgbe->param_en_1000fdx_cap = 1;
3539 ixgbe->param_adv_1000fdx_cap = 1;
3541 ixgbe->param_en_1000fdx_cap = 0;
3542 ixgbe->param_adv_1000fdx_cap = 0;
3546 ixgbe->param_en_100fdx_cap = 1;
3547 ixgbe->param_adv_100fdx_cap = 1;
3549 ixgbe->param_en_100fdx_cap = 0;
3550 ixgbe->param_adv_100fdx_cap = 0;
3553 ixgbe->param_pause_cap = 1;
3554 ixgbe->param_asym_pause_cap = 1;
3555 ixgbe->param_rem_fault = 0;
3557 ixgbe->param_adv_autoneg_cap = 1;
3558 ixgbe->param_adv_pause_cap = 1;
3559 ixgbe->param_adv_asym_pause_cap = 1;
3560 ixgbe->param_adv_rem_fault = 0;
3562 ixgbe->param_lp_10000fdx_cap = 0;
3563 ixgbe->param_lp_5000fdx_cap = 0;
3564 ixgbe->param_lp_2500fdx_cap = 0;
3565 ixgbe->param_lp_1000fdx_cap = 0;
3566 ixgbe->param_lp_100fdx_cap = 0;
3567 ixgbe->param_lp_autoneg_cap = 0;
3568 ixgbe->param_lp_pause_cap = 0;
3569 ixgbe->param_lp_asym_pause_cap = 0;
3570 ixgbe->param_lp_rem_fault = 0;
3575 * ixgbe.conf.
3584 ixgbe_get_prop(ixgbe_t *ixgbe,
3595 value = ddi_prop_get_int(DDI_DEV_T_ANY, ixgbe->dip,
3610 ixgbe_driver_setup_link(ixgbe_t *ixgbe, boolean_t setup_hw)
3612 struct ixgbe_hw *hw = &ixgbe->hw;
3618 if (ixgbe->param_en_10000fdx_cap == 1)
3621 if (ixgbe->param_en_5000fdx_cap == 1)
3624 if (ixgbe->param_en_2500fdx_cap == 1)
3627 if (ixgbe->param_en_1000fdx_cap == 1)
3630 if (ixgbe->param_en_100fdx_cap == 1)
3636 if (ixgbe->param_adv_autoneg_cap == 1 && advertised == 0) {
3637 ixgbe_notice(ixgbe, "Invalid link settings. Setting link "
3647 if (ixgbe_setup_link(&ixgbe->hw, advertised,
3648 ixgbe->param_adv_autoneg_cap) != IXGBE_SUCCESS) {
3649 ixgbe_notice(ixgbe, "Setup link failed on this "
3664 ixgbe_driver_link_check(ixgbe_t *ixgbe)
3666 struct ixgbe_hw *hw = &ixgbe->hw;
3671 ASSERT(mutex_owned(&ixgbe->gen_lock));
3675 ixgbe->link_check_complete = B_TRUE;
3683 if (ixgbe->link_state != LINK_STATE_UP) {
3686 ixgbe->link_speed = SPEED_10GB;
3689 ixgbe->link_speed = SPEED_5GB;
3692 ixgbe->link_speed = SPEED_2_5GB;
3695 ixgbe->link_speed = SPEED_1GB;
3698 ixgbe->link_speed = SPEED_100;
3700 ixgbe->link_duplex = LINK_DUPLEX_FULL;
3701 ixgbe->link_state = LINK_STATE_UP;
3705 if (ixgbe->link_check_complete == B_TRUE ||
3706 (ixgbe->link_check_complete == B_FALSE &&
3707 gethrtime() >= ixgbe->link_check_hrtime)) {
3711 ixgbe->link_check_complete = B_TRUE;
3713 if (ixgbe->link_state != LINK_STATE_DOWN) {
3714 ixgbe->link_speed = 0;
3715 ixgbe->link_duplex = LINK_DUPLEX_UNKNOWN;
3716 ixgbe->link_state = LINK_STATE_DOWN;
3727 ixgbe->eims |= IXGBE_EICR_LSC;
3728 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
3732 mac_link_update(ixgbe->mac_hdl, ixgbe->link_state);
3742 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3743 uint32_t eicr = ixgbe->eicr;
3744 struct ixgbe_hw *hw = &ixgbe->hw;
3746 mutex_enter(&ixgbe->gen_lock);
3754 ixgbe_driver_link_check(ixgbe);
3755 ixgbe_get_hw_state(ixgbe);
3766 ixgbe_driver_link_check(ixgbe);
3767 ixgbe_get_hw_state(ixgbe);
3769 mutex_exit(&ixgbe->gen_lock);
3774 ixgbe->link_check_complete = B_FALSE;
3775 ixgbe->link_check_hrtime = gethrtime() +
3789 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3790 struct ixgbe_hw *hw = &ixgbe->hw;
3791 uint32_t eicr = ixgbe->eicr;
3795 mutex_enter(&ixgbe->gen_lock);
3804 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_OVERTEMP);
3809 ixgbe_disable_adapter_interrupts(ixgbe);
3816 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
3817 ixgbe_error(ixgbe,
3820 ixgbe_error(ixgbe,
3830 mutex_exit(&ixgbe->gen_lock);
3845 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3846 struct ixgbe_hw *hw = &ixgbe->hw;
3849 mutex_enter(&ixgbe->gen_lock);
3867 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_OVERTEMP);
3872 ixgbe_disable_adapter_interrupts(ixgbe);
3879 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
3880 ixgbe_error(ixgbe,
3883 ixgbe_error(ixgbe,
3889 mutex_exit(&ixgbe->gen_lock);
3898 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3900 mutex_enter(&ixgbe->gen_lock);
3901 ixgbe_driver_link_check(ixgbe);
3902 mutex_exit(&ixgbe->gen_lock);
3913 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3915 if (ixgbe->ixgbe_state & IXGBE_OVERTEMP)
3918 if (ixgbe->ixgbe_state & IXGBE_ERROR) {
3919 ixgbe->reset_count++;
3920 if (ixgbe_reset(ixgbe) == IXGBE_SUCCESS)
3921 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_RESTORED);
3925 if (ixgbe_stall_check(ixgbe)) {
3926 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_STALL);
3927 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
3929 ixgbe->reset_count++;
3930 if (ixgbe_reset(ixgbe) == IXGBE_SUCCESS)
3931 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_RESTORED);
3935 ixgbe_restart_watchdog_timer(ixgbe);
3946 * value exceeds the threshold, the ixgbe is assumed to
3950 ixgbe_stall_check(ixgbe_t *ixgbe)
3956 if (ixgbe->link_state != LINK_STATE_UP)
3963 for (i = 0; i < ixgbe->num_tx_rings; i++) {
3964 tx_ring = &ixgbe->tx_rings[i];
3965 if (tx_ring->tbd_free <= ixgbe->tx_recycle_thresh) {
4007 ixgbe_find_mac_address(ixgbe_t *ixgbe)
4010 struct ixgbe_hw *hw = &ixgbe->hw;
4026 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip,
4041 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip, 0,
4058 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip,
4074 _NOTE(ARGUNUSED(ixgbe));
4082 ixgbe_arm_watchdog_timer(ixgbe_t *ixgbe)
4087 ixgbe->watchdog_tid =
4089 (void *)ixgbe, 1 * drv_usectohz(1000000));
4097 ixgbe_enable_watchdog_timer(ixgbe_t *ixgbe)
4099 mutex_enter(&ixgbe->watchdog_lock);
4101 if (!ixgbe->watchdog_enable) {
4102 ixgbe->watchdog_enable = B_TRUE;
4103 ixgbe->watchdog_start = B_TRUE;
4104 ixgbe_arm_watchdog_timer(ixgbe);
4107 mutex_exit(&ixgbe->watchdog_lock);
4114 ixgbe_disable_watchdog_timer(ixgbe_t *ixgbe)
4118 mutex_enter(&ixgbe->watchdog_lock);
4120 ixgbe->watchdog_enable = B_FALSE;
4121 ixgbe->watchdog_start = B_FALSE;
4122 tid = ixgbe->watchdog_tid;
4123 ixgbe->watchdog_tid = 0;
4125 mutex_exit(&ixgbe->watchdog_lock);
4135 ixgbe_start_watchdog_timer(ixgbe_t *ixgbe)
4137 mutex_enter(&ixgbe->watchdog_lock);
4139 if (ixgbe->watchdog_enable) {
4140 if (!ixgbe->watchdog_start) {
4141 ixgbe->watchdog_start = B_TRUE;
4142 ixgbe_arm_watchdog_timer(ixgbe);
4146 mutex_exit(&ixgbe->watchdog_lock);
4153 ixgbe_restart_watchdog_timer(ixgbe_t *ixgbe)
4155 mutex_enter(&ixgbe->watchdog_lock);
4157 if (ixgbe->watchdog_start)
4158 ixgbe_arm_watchdog_timer(ixgbe);
4160 mutex_exit(&ixgbe->watchdog_lock);
4167 ixgbe_stop_watchdog_timer(ixgbe_t *ixgbe)
4171 mutex_enter(&ixgbe->watchdog_lock);
4173 ixgbe->watchdog_start = B_FALSE;
4174 tid = ixgbe->watchdog_tid;
4175 ixgbe->watchdog_tid = 0;
4177 mutex_exit(&ixgbe->watchdog_lock);
4187 ixgbe_disable_adapter_interrupts(ixgbe_t *ixgbe)
4189 struct ixgbe_hw *hw = &ixgbe->hw;
4199 if (ixgbe->intr_type == DDI_INTR_TYPE_MSIX) {
4210 ixgbe_enable_adapter_interrupts(ixgbe_t *ixgbe)
4212 struct ixgbe_hw *hw = &ixgbe->hw;
4217 ixgbe->eims = IXGBE_EIMS_ENABLE_MASK; /* shared code default */
4218 ixgbe->eims &= ~IXGBE_EIMS_TCP_TIMER; /* minus tcp timer */
4219 ixgbe->eims |= ixgbe->capab->other_intr; /* "other" interrupt types */
4222 eiam = ixgbe->capab->other_intr;
4227 if (ixgbe->intr_type == DDI_INTR_TYPE_MSIX) {
4229 eiac = (ixgbe->eims & ~IXGBE_OTHER_INTR);
4250 (ixgbe->intr_type == DDI_INTR_TYPE_MSI)) {
4258 gpie |= ixgbe->capab->other_gpie;
4265 gpie |= ixgbe->capab->other_gpie;
4268 if (ixgbe->lro_enable) {
4278 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4289 ixgbe_loopback_ioctl(ixgbe_t *ixgbe, struct iocblk *iocp, mblk_t *mp)
4340 *lbmp = ixgbe->loopback_mode;
4349 if (!ixgbe_set_loopback_mode(ixgbe, *lbmp))
4357 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
4358 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
4369 ixgbe_set_loopback_mode(ixgbe_t *ixgbe, uint32_t mode)
4371 if (mode == ixgbe->loopback_mode)
4374 ixgbe->loopback_mode = mode;
4380 (void) ixgbe_reset(ixgbe);
4384 mutex_enter(&ixgbe->gen_lock);
4388 mutex_exit(&ixgbe->gen_lock);
4395 ixgbe_set_internal_mac_loopback(ixgbe);
4399 mutex_exit(&ixgbe->gen_lock);
4408 ixgbe_set_internal_mac_loopback(ixgbe_t *ixgbe)
4414 hw = &ixgbe->hw;
4419 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_HLREG0);
4421 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_HLREG0, reg);
4423 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC);
4425 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_AUTOC, reg);
4432 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_LPBK,
4435 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_LPBK,
4438 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_10G,
4441 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_10G,
4444 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_1G,
4447 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_1G,
4450 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_AN,
4453 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_AN,
4461 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC);
4464 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_AUTOC, reg);
4466 (void) ixgbe_setup_link(&ixgbe->hw, IXGBE_LINK_SPEED_10GB_FULL,
4490 mac_rx_ring(rx_ring->ixgbe->mac_hdl, rx_ring->ring_handle, mp,
4501 ixgbe_t *ixgbe = tx_ring->ixgbe;
4512 (tx_ring->tbd_free >= ixgbe->tx_resched_thresh)) {
4514 mac_tx_ring_update(tx_ring->ixgbe->mac_hdl,
4525 ixgbe_intr_other_work(ixgbe_t *ixgbe, uint32_t eicr)
4527 struct ixgbe_hw *hw = &ixgbe->hw;
4529 ASSERT(mutex_owned(&ixgbe->gen_lock));
4535 ixgbe_driver_link_check(ixgbe);
4536 ixgbe_get_hw_state(ixgbe);
4542 if ((ixgbe->capab->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
4544 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_OVERTEMP);
4549 ixgbe_disable_adapter_interrupts(ixgbe);
4554 (void) ixgbe_stop_adapter(&ixgbe->hw);
4556 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
4557 ixgbe_error(ixgbe,
4560 ixgbe_error(ixgbe,
4564 ixgbe->eims |= IXGBE_EICR_GPI_SDP1;
4570 if ((ixgbe->capab->flags & IXGBE_FLAG_SFP_PLUG_CAPABLE) &&
4573 ixgbe->eicr = eicr;
4574 if ((ddi_taskq_dispatch(ixgbe->sfp_taskq,
4575 ixgbe_sfp_check, (void *)ixgbe,
4577 ixgbe_log(ixgbe, "No memory available to dispatch "
4585 if ((ixgbe->capab->flags & IXGBE_FLAG_TEMP_SENSOR_CAPABLE) &&
4588 ixgbe->eicr = eicr;
4589 if ((ddi_taskq_dispatch(ixgbe->overtemp_taskq,
4590 ixgbe_overtemp_check, (void *)ixgbe,
4592 ixgbe_log(ixgbe, "No memory available to dispatch "
4602 ixgbe->eicr = eicr;
4603 if ((ddi_taskq_dispatch(ixgbe->phy_taskq,
4604 ixgbe_phy_check, (void *)ixgbe,
4606 ixgbe_log(ixgbe, "No memory available to dispatch "
4618 ixgbe_t *ixgbe = (ixgbe_t *)arg1;
4619 struct ixgbe_hw *hw = &ixgbe->hw;
4629 mutex_enter(&ixgbe->gen_lock);
4630 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
4631 mutex_exit(&ixgbe->gen_lock);
4643 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
4644 mutex_exit(&ixgbe->gen_lock);
4645 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
4646 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR);
4655 ASSERT(ixgbe->num_rx_rings == 1);
4656 ASSERT(ixgbe->num_tx_rings == 1);
4662 ixgbe->eimc |= IXGBE_EICR_RTX_QUEUE;
4663 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
4664 ixgbe->eims |= IXGBE_EICR_RTX_QUEUE;
4668 rx_ring = &ixgbe->rx_rings[0];
4679 tx_ring = &ixgbe->tx_rings[0];
4686 (tx_ring->tbd_free >= ixgbe->tx_resched_thresh));
4690 if (eicr & ixgbe->capab->other_intr) {
4693 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4700 ixgbe->eimc = IXGBE_82599_OTHER_INTR;
4701 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
4707 ixgbe_intr_other_work(ixgbe, eicr);
4708 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4711 mutex_exit(&ixgbe->gen_lock);
4715 mutex_exit(&ixgbe->gen_lock);
4724 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4730 mac_rx_ring(rx_ring->ixgbe->mac_hdl, rx_ring->ring_handle, mp,
4736 mac_tx_ring_update(ixgbe->mac_hdl, tx_ring->ring_handle);
4749 ixgbe_t *ixgbe = (ixgbe_t *)arg1;
4750 struct ixgbe_hw *hw = &ixgbe->hw;
4757 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
4758 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
4759 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR);
4767 ASSERT(ixgbe->num_rx_rings == 1);
4768 ASSERT(ixgbe->num_tx_rings == 1);
4774 ixgbe_intr_rx_work(&ixgbe->rx_rings[0]);
4781 ixgbe_intr_tx_work(&ixgbe->tx_rings[0]);
4785 if (eicr & ixgbe->capab->other_intr) {
4786 mutex_enter(&ixgbe->gen_lock);
4789 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4796 ixgbe->eimc = IXGBE_82599_OTHER_INTR;
4797 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
4803 ixgbe_intr_other_work(ixgbe, eicr);
4804 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4805 mutex_exit(&ixgbe->gen_lock);
4809 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4821 ixgbe_t *ixgbe = vect->ixgbe;
4822 struct ixgbe_hw *hw = &ixgbe->hw;
4831 r_idx = bt_getlowbit(vect->rx_map, 0, (ixgbe->num_rx_rings - 1));
4833 ixgbe_intr_rx_work(&ixgbe->rx_rings[r_idx]);
4835 (ixgbe->num_rx_rings - 1));
4841 r_idx = bt_getlowbit(vect->tx_map, 0, (ixgbe->num_tx_rings - 1));
4843 ixgbe_intr_tx_work(&ixgbe->tx_rings[r_idx]);
4845 (ixgbe->num_tx_rings - 1));
4855 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) !=
4857 ddi_fm_service_impact(ixgbe->dip,
4859 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR);
4866 if (eicr & ixgbe->capab->other_intr) {
4867 mutex_enter(&ixgbe->gen_lock);
4870 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4871 ixgbe_intr_other_work(ixgbe, eicr);
4878 ixgbe->eims |= IXGBE_EICR_RTX_QUEUE;
4879 ixgbe_intr_other_work(ixgbe, eicr);
4885 mutex_exit(&ixgbe->gen_lock);
4889 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4900 * ixgbe->intr_force can be used to force sequence to start with
4905 ixgbe_alloc_intrs(ixgbe_t *ixgbe)
4911 devinfo = ixgbe->dip;
4919 ixgbe_log(ixgbe,
4923 IXGBE_DEBUGLOG_1(ixgbe, "Supported interrupt types: %x", intr_types);
4925 ixgbe->intr_type = 0;
4931 (ixgbe->intr_force <= IXGBE_INTR_MSIX)) {
4932 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_MSIX);
4936 ixgbe_log(ixgbe,
4943 ixgbe->num_rx_rings = 1;
4944 ixgbe->num_rx_groups = 1;
4945 ixgbe->num_tx_rings = 1;
4946 ixgbe->classify_mode = IXGBE_CLASSIFY_NONE;
4947 ixgbe_log(ixgbe,
4954 (ixgbe->intr_force <= IXGBE_INTR_MSI)) {
4955 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_MSI);
4959 ixgbe_log(ixgbe,
4975 if (ixgbe->hw.mac.type == ixgbe_mac_X550 ||
4976 ixgbe->hw.mac.type == ixgbe_mac_X550EM_x ||
4977 ixgbe->hw.mac.type == ixgbe_mac_X550_vf ||
4978 ixgbe->hw.mac.type == ixgbe_mac_X550EM_x_vf) {
4979 ixgbe_log(ixgbe,
4984 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_FIXED);
4988 ixgbe_log(ixgbe,
5007 ixgbe_alloc_intr_handles(ixgbe_t *ixgbe, int intr_type)
5015 devinfo = ixgbe->dip;
5021 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: legacy");
5027 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: MSI");
5036 request = min(16, ixgbe->num_rx_rings + ixgbe->num_tx_rings);
5037 if (request > ixgbe->capab->max_ring_vect)
5038 request = ixgbe->capab->max_ring_vect;
5040 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: MSI-X");
5044 ixgbe_log(ixgbe,
5049 IXGBE_DEBUGLOG_2(ixgbe, "interrupt handles requested: %d minimum: %d",
5057 ixgbe_log(ixgbe,
5062 IXGBE_DEBUGLOG_1(ixgbe, "interrupts supported: %d", count);
5065 ixgbe->intr_cnt = 0;
5066 ixgbe->intr_cnt_max = 0;
5067 ixgbe->intr_cnt_min = 0;
5072 ixgbe->intr_size = request * sizeof (ddi_intr_handle_t);
5073 ixgbe->htable = kmem_alloc(ixgbe->intr_size, KM_SLEEP);
5075 rc = ddi_intr_alloc(devinfo, ixgbe->htable, intr_type, 0,
5078 ixgbe_log(ixgbe, "Allocate interrupts failed. "
5083 IXGBE_DEBUGLOG_1(ixgbe, "interrupts actually allocated: %d", actual);
5088 ixgbe->intr_cnt = actual;
5089 ixgbe->intr_cnt_max = request;
5090 ixgbe->intr_cnt_min = minimum;
5096 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
5097 ASSERT((ixgbe->num_rx_rings % ixgbe->num_rx_groups) == 0);
5099 ixgbe->num_rx_rings = ixgbe->num_rx_groups * actual;
5100 ixgbe_setup_vmdq_rss_conf(ixgbe);
5108 ixgbe_log(ixgbe, "Insufficient interrupt handles available: %d",
5116 rc = ddi_intr_get_pri(ixgbe->htable[0], &ixgbe->intr_pri);
5118 ixgbe_log(ixgbe,
5123 rc = ddi_intr_get_cap(ixgbe->htable[0], &ixgbe->intr_cap);
5125 ixgbe_log(ixgbe,
5130 ixgbe->intr_type = intr_type;
5135 ixgbe_rem_intrs(ixgbe);
5147 ixgbe_add_intr_handlers(ixgbe_t *ixgbe)
5152 switch (ixgbe->intr_type) {
5157 for (vector = 0; vector < ixgbe->intr_cnt; vector++) {
5161 rc = ddi_intr_add_handler(ixgbe->htable[vector],
5163 (void *)&ixgbe->vect_map[vector], NULL);
5166 ixgbe_log(ixgbe,
5171 ixgbe->htable[vector]);
5183 rc = ddi_intr_add_handler(ixgbe->htable[vector],
5185 (void *)ixgbe, NULL);
5188 ixgbe_log(ixgbe,
5199 rc = ddi_intr_add_handler(ixgbe->htable[vector],
5201 (void *)ixgbe, NULL);
5204 ixgbe_log(ixgbe,
5223 ixgbe_map_rxring_to_vector(ixgbe_t *ixgbe, int r_idx, int v_idx)
5228 BT_SET(ixgbe->vect_map[v_idx].rx_map, r_idx);
5233 ixgbe->vect_map[v_idx].rxr_cnt++;
5238 ixgbe->rx_rings[r_idx].intr_vector = v_idx;
5239 ixgbe->rx_rings[r_idx].vect_bit = 1 << v_idx;
5247 ixgbe_map_txring_to_vector(ixgbe_t *ixgbe, int t_idx, int v_idx)
5252 BT_SET(ixgbe->vect_map[v_idx].tx_map, t_idx);
5257 ixgbe->vect_map[v_idx].txr_cnt++;
5262 ixgbe->tx_rings[t_idx].intr_vector = v_idx;
5263 ixgbe->tx_rings[t_idx].vect_bit = 1 << v_idx;
5275 ixgbe_setup_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, uint8_t msix_vector,
5278 struct ixgbe_hw *hw = &ixgbe->hw;
5333 ixgbe_enable_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, int8_t cause)
5335 struct ixgbe_hw *hw = &ixgbe->hw;
5385 ixgbe_disable_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, int8_t cause)
5387 struct ixgbe_hw *hw = &ixgbe->hw;
5433 ixgbe_get_hw_rx_index(ixgbe_t *ixgbe, uint32_t sw_rx_index)
5436 struct ixgbe_hw *hw = &ixgbe->hw;
5439 if (ixgbe->classify_mode == IXGBE_CLASSIFY_RSS ||
5440 ixgbe->classify_mode == IXGBE_CLASSIFY_NONE) {
5442 } else if (ixgbe->classify_mode == IXGBE_CLASSIFY_VMDQ) {
5456 } else if (ixgbe->classify_mode == IXGBE_CLASSIFY_VMDQ_RSS) {
5457 rx_ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
5469 if (ixgbe->num_rx_groups > 32) {
5498 ixgbe_map_intrs_to_vectors(ixgbe_t *ixgbe)
5503 bzero(&ixgbe->vect_map, sizeof (ixgbe->vect_map));
5504 for (i = 0; i < ixgbe->intr_cnt; i++) {
5505 ixgbe->vect_map[i].ixgbe = ixgbe;
5512 if (ixgbe->intr_type != DDI_INTR_TYPE_MSIX) {
5513 ixgbe_map_rxring_to_vector(ixgbe, 0, 0);
5514 ixgbe_map_txring_to_vector(ixgbe, 0, 1);
5526 BT_SET(ixgbe->vect_map[vector].other_map, 0);
5527 ixgbe->vect_map[vector].other_cnt++;
5532 for (i = 0; i < ixgbe->num_rx_rings; i++) {
5533 ixgbe_map_rxring_to_vector(ixgbe, i, vector);
5534 vector = (vector +1) % ixgbe->intr_cnt;
5540 for (i = 0; i < ixgbe->num_tx_rings; i++) {
5541 ixgbe_map_txring_to_vector(ixgbe, i, vector);
5542 vector = (vector +1) % ixgbe->intr_cnt;
5555 ixgbe_setup_adapter_vector(ixgbe_t *ixgbe)
5557 struct ixgbe_hw *hw = &ixgbe->hw;
5589 if (ixgbe->intr_type != DDI_INTR_TYPE_MSIX) {
5590 ixgbe_setup_ivar(ixgbe, 0, 0, 0);
5591 ixgbe_setup_ivar(ixgbe, 0, 1, 1);
5598 ixgbe_setup_ivar(ixgbe, IXGBE_IVAR_OTHER_CAUSES_INDEX, 0, -1);
5603 for (v_idx = 0; v_idx < ixgbe->intr_cnt; v_idx++) {
5604 vect = &ixgbe->vect_map[v_idx];
5610 (ixgbe->num_rx_rings - 1));
5613 hw_index = ixgbe->rx_rings[r_idx].hw_index;
5614 ixgbe_setup_ivar(ixgbe, hw_index, v_idx, 0);
5616 (ixgbe->num_rx_rings - 1));
5623 (ixgbe->num_tx_rings - 1));
5626 ixgbe_setup_ivar(ixgbe, r_idx, v_idx, 1);
5628 (ixgbe->num_tx_rings - 1));
5637 ixgbe_rem_intr_handlers(ixgbe_t *ixgbe)
5642 for (i = 0; i < ixgbe->intr_cnt; i++) {
5643 rc = ddi_intr_remove_handler(ixgbe->htable[i]);
5645 IXGBE_DEBUGLOG_1(ixgbe,
5655 ixgbe_rem_intrs(ixgbe_t *ixgbe)
5660 for (i = 0; i < ixgbe->intr_cnt; i++) {
5661 rc = ddi_intr_free(ixgbe->htable[i]);
5663 IXGBE_DEBUGLOG_1(ixgbe,
5668 kmem_free(ixgbe->htable, ixgbe->intr_size);
5669 ixgbe->htable = NULL;
5676 ixgbe_enable_intrs(ixgbe_t *ixgbe)
5684 if (ixgbe->intr_cap & DDI_INTR_FLAG_BLOCK) {
5688 rc = ddi_intr_block_enable(ixgbe->htable, ixgbe->intr_cnt);
5690 ixgbe_log(ixgbe,
5698 for (i = 0; i < ixgbe->intr_cnt; i++) {
5699 rc = ddi_intr_enable(ixgbe->htable[i]);
5701 ixgbe_log(ixgbe,
5715 ixgbe_disable_intrs(ixgbe_t *ixgbe)
5723 if (ixgbe->intr_cap & DDI_INTR_FLAG_BLOCK) {
5724 rc = ddi_intr_block_disable(ixgbe->htable, ixgbe->intr_cnt);
5726 ixgbe_log(ixgbe,
5731 for (i = 0; i < ixgbe->intr_cnt; i++) {
5732 rc = ddi_intr_disable(ixgbe->htable[i]);
5734 ixgbe_log(ixgbe,
5748 ixgbe_get_hw_state(ixgbe_t *ixgbe)
5750 struct ixgbe_hw *hw = &ixgbe->hw;
5755 ASSERT(mutex_owned(&ixgbe->gen_lock));
5756 ixgbe->param_lp_1000fdx_cap = 0;
5757 ixgbe->param_lp_100fdx_cap = 0;
5770 ixgbe->param_lp_1000fdx_cap =
5772 ixgbe->param_lp_100fdx_cap =
5794 speed = ixgbe->speeds_supported;
5796 ixgbe->param_adv_10000fdx_cap =
5798 ixgbe->param_adv_5000fdx_cap =
5800 ixgbe->param_adv_2500fdx_cap =
5802 ixgbe->param_adv_1000fdx_cap =
5804 ixgbe->param_adv_100fdx_cap =
5918 ixgbe_fm_init(ixgbe_t *ixgbe)
5926 if (ixgbe->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
5932 if (ixgbe->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
5940 if (ixgbe->fm_capabilities) {
5945 ddi_fm_init(ixgbe->dip, &ixgbe->fm_capabilities, &iblk);
5950 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities) ||
5951 DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
5952 pci_ereport_setup(ixgbe->dip);
5957 if (DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
5958 ddi_fm_handler_register(ixgbe->dip,
5959 ixgbe_fm_error_cb, (void*) ixgbe);
5964 ixgbe_fm_fini(ixgbe_t *ixgbe)
5969 if (ixgbe->fm_capabilities) {
5974 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities) ||
5975 DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
5976 pci_ereport_teardown(ixgbe->dip);
5981 if (DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
5982 ddi_fm_handler_unregister(ixgbe->dip);
5987 ddi_fm_fini(ixgbe->dip);
5992 ixgbe_fm_ereport(ixgbe_t *ixgbe, char *detail)
5999 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities)) {
6000 ddi_fm_ereport_post(ixgbe->dip, buf, ena, DDI_NOSLEEP,
6020 ixgbe_get_rx_ring_index(ixgbe_t *ixgbe, int gindex, int rindex)
6025 for (i = 0; i < ixgbe->num_rx_rings; i++) {
6026 rx_ring = &ixgbe->rx_rings[i];
6044 ixgbe_t *ixgbe = (ixgbe_t *)arg;
6054 ixgbe, group_index, ring_index);
6058 ixgbe_rx_ring_t *rx_ring = &ixgbe->rx_rings[global_ring_index];
6070 if (ixgbe->intr_type &
6073 ixgbe->htable[rx_ring->intr_vector];
6080 ASSERT(ring_index < ixgbe->num_tx_rings);
6082 ixgbe_tx_ring_t *tx_ring = &ixgbe->tx_rings[ring_index];
6090 if (ixgbe->intr_type &
6093 ixgbe->htable[tx_ring->intr_vector];
6109 ixgbe_t *ixgbe = (ixgbe_t *)arg;
6115 rx_group = &ixgbe->rx_groups[index];
6123 infop->mgi_count = (ixgbe->num_rx_rings / ixgbe->num_rx_groups);
6141 ixgbe_t *ixgbe = rx_ring->ixgbe;
6146 mutex_enter(&ixgbe->gen_lock);
6147 if (ixgbe->ixgbe_state & IXGBE_INTR_ADJUST) {
6148 mutex_exit(&ixgbe->gen_lock);
6162 ixgbe_enable_ivar(ixgbe, hw_r_idx, 0);
6164 BT_SET(ixgbe->vect_map[v_idx].rx_map, r_idx);
6169 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_EICS, (1 << v_idx));
6170 IXGBE_WRITE_FLUSH(&ixgbe->hw);
6172 mutex_exit(&ixgbe->gen_lock);
6184 ixgbe_t *ixgbe = rx_ring->ixgbe;
6189 mutex_enter(&ixgbe->gen_lock);
6190 if (ixgbe->ixgbe_state & IXGBE_INTR_ADJUST) {
6191 mutex_exit(&ixgbe->gen_lock);
6213 ixgbe_disable_ivar(ixgbe, hw_r_idx, 0);
6215 BT_CLEAR(ixgbe->vect_map[v_idx].rx_map, r_idx);
6217 mutex_exit(&ixgbe->gen_lock);
6229 ixgbe_t *ixgbe = rx_group->ixgbe;
6230 struct ixgbe_hw *hw = &ixgbe->hw;
6233 mutex_enter(&ixgbe->gen_lock);
6235 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
6236 mutex_exit(&ixgbe->gen_lock);
6240 if (ixgbe->unicst_avail == 0) {
6242 mutex_exit(&ixgbe->gen_lock);
6247 * The first ixgbe->num_rx_groups slots are reserved for each respective
6253 if (ixgbe->unicst_addr[rx_group->index].mac.set == 1) {
6254 for (i = ixgbe->num_rx_groups; i < ixgbe->unicst_total; i++) {
6255 if (ixgbe->unicst_addr[i].mac.set == 0) {
6266 mutex_exit(&ixgbe->gen_lock);
6270 bcopy(mac_addr, ixgbe->unicst_addr[slot].mac.addr, ETHERADDRL);
6271 (void) ixgbe_set_rar(hw, slot, ixgbe->unicst_addr[slot].mac.addr,
6273 ixgbe->unicst_addr[slot].mac.set = 1;
6274 ixgbe->unicst_addr[slot].mac.group_index = rx_group->index;
6275 ixgbe->unicst_avail--;
6277 mutex_exit(&ixgbe->gen_lock);
6289 ixgbe_t *ixgbe = rx_group->ixgbe;
6290 struct ixgbe_hw *hw = &ixgbe->hw;
6293 mutex_enter(&ixgbe->gen_lock);
6295 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
6296 mutex_exit(&ixgbe->gen_lock);
6300 slot = ixgbe_unicst_find(ixgbe, mac_addr);
6302 mutex_exit(&ixgbe->gen_lock);
6306 if (ixgbe->unicst_addr[slot].mac.set == 0) {
6307 mutex_exit(&ixgbe->gen_lock);
6311 bzero(ixgbe->unicst_addr[slot].mac.addr, ETHERADDRL);
6313 ixgbe->unicst_addr[slot].mac.set = 0;
6314 ixgbe->unicst_avail++;
6316 mutex_exit(&ixgbe->gen_lock);