Lines Matching defs:hw
42 * @hw: pointer to hardware structure
48 s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
62 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
64 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc));
66 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);
68 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
70 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc));
72 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);
75 stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc));
83 * @hw: pointer to hardware structure
89 s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
102 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
104 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
112 * @hw: pointer to hardware structure
117 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
131 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
143 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
156 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
164 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
171 * @hw: pointer to hardware structure
176 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
184 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
185 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
201 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
209 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
216 * @hw: pointer to hardware structure
221 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
235 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
247 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
261 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
270 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
277 * @hw: pointer to hardware structure
283 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
289 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
292 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
302 if (hw->mac.type >= ixgbe_mac_X540)
308 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
328 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
329 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
330 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
339 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
340 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
343 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
347 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
348 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
352 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
354 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
357 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
364 * @hw: pointer to hardware structure
369 s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw,
395 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
423 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
440 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
460 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
472 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100);
482 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100);
490 * @hw: pointer to hardware structure
495 s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
502 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
504 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
506 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
541 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
552 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
556 IXGBE_WRITE_REG(hw, IXGBE_QDE,
560 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
562 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
565 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
567 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
574 * @hw: pointer to hardware structure
579 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,
585 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
587 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
589 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,