Cross Reference: /illumos-gate/usr/src/uts/common/io/ixgbe/core/ixgbe_dcb

Lines Matching defs:hw
42  * @hw: pointer to hardware structure
48 s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
62 		stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
64 		stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
66 		stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
68 		stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
84  * @hw: pointer to hardware structure
90 s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
103 		stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
105 		stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
113  * @hw: pointer to hardware structure
118 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
126 	reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
127 	IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
129 	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
137 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
149 		IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
152 	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
156 	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
158 	reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
161 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
168  * @hw: pointer to hardware structure
173 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
180 	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
189 	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
204 		IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
212  * @hw: pointer to hardware structure
217 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
224 	reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
230 	IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
244 		IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
248 	reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
250 	IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
257  * @hw: pointer to hardware structure
262 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
268 	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
271 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
274 	reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
280 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
285 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
286 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
290 		fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
291 		reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
292 		IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
293 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
297 	reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
299 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
302 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
309  * @hw: pointer to hardware structure
314 s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
322 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
324 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
325 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
327 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
331 		reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
333 		IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
341  * @hw: pointer to hardware structure
346 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed,
352 	ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
353 	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
355 	ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
357 	ixgbe_dcb_config_tc_stats_82598(hw);