Lines Matching defs:sc
471 iwp_sc_t *sc;
487 sc = ddi_get_soft_state(iwp_soft_state_p,
489 ASSERT(sc != NULL);
491 if (sc->sc_flags & IWP_F_RUNNING) {
492 (void) iwp_init(sc);
495 atomic_and_32(&sc->sc_flags, ~IWP_F_SUSPEND);
512 sc = ddi_get_soft_state(iwp_soft_state_p, instance);
513 ASSERT(sc != NULL);
515 sc->sc_dip = dip;
520 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0,
521 &iwp_reg_accattr, &sc->sc_cfg_handle);
528 sc->sc_dev_id = ddi_get16(sc->sc_cfg_handle,
529 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID));
530 if ((sc->sc_dev_id != 0x422B) &&
531 (sc->sc_dev_id != 0x422C) &&
532 (sc->sc_dev_id != 0x4238) &&
533 (sc->sc_dev_id != 0x4239) &&
534 (sc->sc_dev_id != 0x008d) &&
535 (sc->sc_dev_id != 0x008e)) {
541 iwp_set_chip_param(sc);
543 sc->sc_rev = ddi_get8(sc->sc_cfg_handle,
544 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID));
549 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base +
555 sc->sc_clsz = ddi_get16(sc->sc_cfg_handle,
556 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
557 if (!sc->sc_clsz) {
558 sc->sc_clsz = 16;
560 sc->sc_clsz = (sc->sc_clsz << 2);
562 sc->sc_dmabuf_sz = roundup(0x1000 + sizeof (struct ieee80211_frame) +
565 IEEE80211_WEP_CRCLEN), sc->sc_clsz);
570 err = ddi_regs_map_setup(dip, 1, &sc->sc_base,
571 0, 0, &iwp_reg_accattr, &sc->sc_handle);
581 sc->sc_hw_rev = IWP_READ(sc, CSR_HW_REV);
597 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
599 err = ddi_intr_alloc(dip, sc->sc_intr_htable, DDI_INTR_TYPE_FIXED, 0,
607 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
614 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER,
615 DDI_INTR_PRI(sc->sc_intr_pri));
616 mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER,
617 DDI_INTR_PRI(sc->sc_intr_pri));
618 mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER,
619 DDI_INTR_PRI(sc->sc_intr_pri));
621 cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL);
622 cv_init(&sc->sc_put_seg_cv, NULL, CV_DRIVER, NULL);
623 cv_init(&sc->sc_ucode_cv, NULL, CV_DRIVER, NULL);
628 cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL);
629 sc->sc_mf_thread = NULL;
630 sc->sc_mf_thread_switch = 0;
635 err = iwp_alloc_shared(sc);
642 (void) memset(sc->sc_shared, 0, sizeof (iwp_shared_t));
647 err = iwp_alloc_kw(sc);
657 err = iwp_preinit(sc);
667 err = iwp_eep_load(sc);
677 sc->sc_eep_calib = (struct iwp_eep_calibration *)
678 iwp_eep_addr_trans(sc, EEP_CALIBRATION);
680 err = iwp_eep_ver_chk(sc);
688 iwp_get_mac_from_eep(sc);
694 err = iwp_ring_init(sc);
701 sc->sc_hdr = (iwp_firmware_hdr_t *)iwp_fw_bin;
706 err = iwp_alloc_fw_dma(sc);
717 ic = &sc->sc_ic;
766 iwp_overwrite_ic_default(sc);
778 err = ddi_intr_add_softint(dip, &sc->sc_soft_hdl, DDI_INTR_SOFTPRI_MAX,
779 iwp_rx_softintr, (caddr_t)sc);
786 err = ddi_intr_add_handler(sc->sc_intr_htable[0], iwp_intr,
787 (caddr_t)sc, NULL);
794 err = ddi_intr_enable(sc->sc_intr_htable[0]);
819 macp->m_driver = sc;
859 sc->sc_mf_thread_switch = 1;
860 if (NULL == sc->sc_mf_thread) {
861 sc->sc_mf_thread = thread_create((caddr_t)NULL, 0,
862 iwp_thread, sc, 0, &p0, TS_RUN, minclsyspri);
865 atomic_or_32(&sc->sc_flags, IWP_F_ATTACHED);
870 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
872 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
874 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
875 sc->sc_soft_hdl = NULL;
879 iwp_free_fw_dma(sc);
881 iwp_ring_free(sc);
883 iwp_free_kw(sc);
885 iwp_free_shared(sc);
887 iwp_destroy_locks(sc);
889 (void) ddi_intr_free(sc->sc_intr_htable[0]);
891 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
893 ddi_regs_map_free(&sc->sc_handle);
895 ddi_regs_map_free(&sc->sc_cfg_handle);
905 iwp_sc_t *sc;
909 sc = ddi_get_soft_state(iwp_soft_state_p, ddi_get_instance(dip));
910 ASSERT(sc != NULL);
911 ic = &sc->sc_ic;
917 atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER);
918 atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL);
920 atomic_or_32(&sc->sc_flags, IWP_F_SUSPEND);
922 if (sc->sc_flags & IWP_F_RUNNING) {
923 iwp_stop(sc);
935 if (!(sc->sc_flags & IWP_F_ATTACHED)) {
942 sc->sc_mf_thread_switch = 0;
944 mutex_enter(&sc->sc_mt_lock);
945 while (sc->sc_mf_thread != NULL) {
946 if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0) {
950 mutex_exit(&sc->sc_mt_lock);
952 err = mac_disable(sc->sc_ic.ic_mach);
960 iwp_stop(sc);
967 iwp_release_calib_buffer(sc);
972 (void) mac_unregister(sc->sc_ic.ic_mach);
974 mutex_enter(&sc->sc_glock);
975 iwp_free_fw_dma(sc);
976 iwp_ring_free(sc);
977 iwp_free_kw(sc);
978 iwp_free_shared(sc);
979 mutex_exit(&sc->sc_glock);
981 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
982 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
983 (void) ddi_intr_free(sc->sc_intr_htable[0]);
984 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
986 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
987 sc->sc_soft_hdl = NULL;
992 ieee80211_detach(&sc->sc_ic);
994 iwp_destroy_locks(sc);
996 ddi_regs_map_free(&sc->sc_handle);
997 ddi_regs_map_free(&sc->sc_cfg_handle);
1008 iwp_destroy_locks(iwp_sc_t *sc)
1010 cv_destroy(&sc->sc_mt_cv);
1011 cv_destroy(&sc->sc_cmd_cv);
1012 cv_destroy(&sc->sc_put_seg_cv);
1013 cv_destroy(&sc->sc_ucode_cv);
1014 mutex_destroy(&sc->sc_mt_lock);
1015 mutex_destroy(&sc->sc_tx_lock);
1016 mutex_destroy(&sc->sc_glock);
1023 iwp_alloc_dma_mem(iwp_sc_t *sc, size_t memsize,
1033 err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p,
1100 iwp_alloc_fw_dma(iwp_sc_t *sc)
1114 if (LE_32(sc->sc_hdr->init_textsz) > RTC_INST_SIZE) {
1117 LE_32(sc->sc_hdr->init_textsz));
1122 if (LE_32(sc->sc_hdr->init_datasz) > RTC_DATA_SIZE) {
1125 LE_32(sc->sc_hdr->init_datasz));
1130 if (LE_32(sc->sc_hdr->textsz) > RTC_INST_SIZE) {
1133 LE_32(sc->sc_hdr->textsz));
1138 if (LE_32(sc->sc_hdr->datasz) > RTC_DATA_SIZE) {
1141 LE_32(sc->sc_hdr->datasz));
1149 t = (char *)(sc->sc_hdr + 1);
1150 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz),
1153 &sc->sc_dma_fw_text);
1160 dma_p = &sc->sc_dma_fw_text;
1167 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->textsz));
1172 t += LE_32(sc->sc_hdr->textsz);
1173 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1176 &sc->sc_dma_fw_data);
1183 dma_p = &sc->sc_dma_fw_data;
1190 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz));
1192 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1195 &sc->sc_dma_fw_data_bak);
1202 dma_p = &sc->sc_dma_fw_data_bak;
1210 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz));
1215 t += LE_32(sc->sc_hdr->datasz);
1216 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_textsz),
1219 &sc->sc_dma_fw_init_text);
1226 dma_p = &sc->sc_dma_fw_init_text;
1234 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_textsz));
1239 t += LE_32(sc->sc_hdr->init_textsz);
1240 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_datasz),
1243 &sc->sc_dma_fw_init_data);
1250 dma_p = &sc->sc_dma_fw_init_data;
1258 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_datasz));
1260 sc->sc_boot = t + LE_32(sc->sc_hdr->init_datasz);
1266 iwp_free_fw_dma(iwp_sc_t *sc)
1268 iwp_free_dma_mem(&sc->sc_dma_fw_text);
1269 iwp_free_dma_mem(&sc->sc_dma_fw_data);
1270 iwp_free_dma_mem(&sc->sc_dma_fw_data_bak);
1271 iwp_free_dma_mem(&sc->sc_dma_fw_init_text);
1272 iwp_free_dma_mem(&sc->sc_dma_fw_init_data);
1279 iwp_alloc_shared(iwp_sc_t *sc)
1289 err = iwp_alloc_dma_mem(sc, sizeof (iwp_shared_t),
1292 &sc->sc_dma_sh);
1297 sc->sc_shared = (iwp_shared_t *)sc->sc_dma_sh.mem_va;
1300 dma_p = &sc->sc_dma_sh;
1309 iwp_free_shared(sc);
1314 iwp_free_shared(iwp_sc_t *sc)
1316 iwp_free_dma_mem(&sc->sc_dma_sh);
1323 iwp_alloc_kw(iwp_sc_t *sc)
1333 err = iwp_alloc_dma_mem(sc, IWP_KW_SIZE,
1336 &sc->sc_dma_kw);
1342 dma_p = &sc->sc_dma_kw;
1351 iwp_free_kw(sc);
1356 iwp_free_kw(iwp_sc_t *sc)
1358 iwp_free_dma_mem(&sc->sc_dma_kw);
1365 iwp_alloc_rx_ring(iwp_sc_t *sc)
1374 ring = &sc->sc_rxq;
1380 err = iwp_alloc_dma_mem(sc, RX_QUEUE_SIZE * sizeof (uint32_t),
1405 err = iwp_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1437 iwp_free_rx_ring(sc);
1445 iwp_reset_rx_ring(iwp_sc_t *sc)
1449 iwp_mac_access_enter(sc);
1450 IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
1452 if (IWP_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24)) {
1463 iwp_mac_access_exit(sc);
1465 sc->sc_rxq.cur = 0;
1469 iwp_free_rx_ring(iwp_sc_t *sc)
1474 if (sc->sc_rxq.data[i].dma_data.dma_hdl) {
1475 IWP_DMA_SYNC(sc->sc_rxq.data[i].dma_data,
1479 iwp_free_dma_mem(&sc->sc_rxq.data[i].dma_data);
1482 if (sc->sc_rxq.dma_desc.dma_hdl) {
1483 IWP_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV);
1486 iwp_free_dma_mem(&sc->sc_rxq.dma_desc);
1493 iwp_alloc_tx_ring(iwp_sc_t *sc, iwp_tx_ring_t *ring,
1515 err = iwp_alloc_dma_mem(sc,
1541 err = iwp_alloc_dma_mem(sc,
1578 err = iwp_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1617 iwp_reset_tx_ring(iwp_sc_t *sc, iwp_tx_ring_t *ring)
1622 iwp_mac_access_enter(sc);
1624 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0);
1626 if (IWP_READ(sc, IWP_FH_TSSR_TX_STATUS_REG) &
1641 iwp_mac_access_exit(sc);
1644 if (!(sc->sc_flags & IWP_F_QUIESCED)) {
1687 iwp_ring_init(iwp_sc_t *sc)
1696 err = iwp_alloc_tx_ring(sc, &sc->sc_txq[i], TFD_TX_CMD_SLOTS,
1706 err = iwp_alloc_tx_ring(sc, &sc->sc_txq[IWP_CMD_QUEUE_NUM],
1712 err = iwp_alloc_rx_ring(sc);
1722 iwp_ring_free(iwp_sc_t *sc)
1726 iwp_free_rx_ring(sc);
1728 iwp_free_tx_ring(&sc->sc_txq[i]);
1790 iwp_sc_t *sc;
1799 sc = (iwp_sc_t *)ic;
1803 mutex_enter(&sc->sc_glock);
1809 atomic_or_32(&sc->sc_flags, IWP_F_SCANNING);
1810 iwp_set_led(sc, 2, 10, 2);
1816 sc->sc_config.assoc_id = 0;
1817 sc->sc_config.filter_flags &=
1823 LE_16(sc->sc_config.chan),
1824 LE_32(sc->sc_config.flags),
1825 LE_32(sc->sc_config.filter_flags)));
1827 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config,
1832 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING);
1833 mutex_exit(&sc->sc_glock);
1841 err = iwp_cmd(sc, REPLY_ADD_STA, &node,
1846 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING);
1847 mutex_exit(&sc->sc_glock);
1852 mutex_exit(&sc->sc_glock);
1854 err = sc->sc_newstate(ic, nstate, arg);
1855 mutex_enter(&sc->sc_glock);
1856 if ((err != 0) || ((err = iwp_scan(sc)) != 0)) {
1859 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING);
1862 mutex_exit(&sc->sc_glock);
1867 sc->sc_clk = 0;
1872 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING);
1878 sc->sc_config.assoc_id = 0;
1879 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
1886 if ((err = iwp_hw_set_before_auth(sc)) != 0) {
1889 mutex_exit(&sc->sc_glock);
1896 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING);
1901 iwp_set_led(sc, 2, 10, 10);
1908 err = iwp_run_state_config(sc);
1912 mutex_exit(&sc->sc_glock);
1920 atomic_or_32(&sc->sc_flags, IWP_F_RATE_AUTO_CTL);
1932 atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL);
1938 iwp_set_led(sc, 2, 0, 1);
1943 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING);
1948 iwp_set_led(sc, 2, 1, 0);
1953 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING);
1958 mutex_exit(&sc->sc_glock);
1960 return (sc->sc_newstate(ic, nstate, arg));
1967 iwp_mac_access_enter(iwp_sc_t *sc)
1972 tmp = IWP_READ(sc, CSR_GP_CNTRL);
1973 IWP_WRITE(sc, CSR_GP_CNTRL,
1978 if ((IWP_READ(sc, CSR_GP_CNTRL) &
1999 iwp_mac_access_exit(iwp_sc_t *sc)
2001 uint32_t tmp = IWP_READ(sc, CSR_GP_CNTRL);
2002 IWP_WRITE(sc, CSR_GP_CNTRL,
2009 * iwp_mem_read(iwp_sc_t *sc, uint32_t addr)
2011 * IWP_WRITE(sc, HBUS_TARG_MEM_RADDR, addr);
2012 * return (IWP_READ(sc, HBUS_TARG_MEM_RDAT));
2020 iwp_mem_write(iwp_sc_t *sc, uint32_t addr, uint32_t data)
2022 IWP_WRITE(sc, HBUS_TARG_MEM_WADDR, addr);
2023 IWP_WRITE(sc, HBUS_TARG_MEM_WDAT, data);
2030 iwp_reg_read(iwp_sc_t *sc, uint32_t addr)
2032 IWP_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24));
2033 return (IWP_READ(sc, HBUS_TARG_PRPH_RDAT));
2040 iwp_reg_write(iwp_sc_t *sc, uint32_t addr, uint32_t data)
2042 IWP_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24));
2043 IWP_WRITE(sc, HBUS_TARG_PRPH_WDAT, data);
2055 iwp_load_init_firmware(iwp_sc_t *sc)
2060 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2065 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_text.cookie.dmac_address,
2066 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_init_text.cookie.dmac_size);
2076 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2077 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2082 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2088 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2093 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_data.cookie.dmac_address,
2094 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_init_data.cookie.dmac_size);
2106 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2107 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2112 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2118 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2124 iwp_load_run_firmware(iwp_sc_t *sc)
2129 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2134 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_text.cookie.dmac_address,
2135 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_text.cookie.dmac_size);
2145 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2146 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2151 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2157 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2162 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_data_bak.cookie.dmac_address,
2163 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_data.cookie.dmac_size);
2175 while (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2176 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) {
2181 if (!(sc->sc_flags & IWP_F_PUT_SEG)) {
2187 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG);
2197 iwp_rx_phy_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc)
2200 sc->sc_rx_phy_res.flag = 1;
2202 (void) memcpy(sc->sc_rx_phy_res.buf, (uint8_t *)(desc + 1),
2211 iwp_rx_mpdu_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc)
2213 ieee80211com_t *ic = &sc->sc_ic;
2215 iwp_rx_ring_t *ring = &sc->sc_rxq;
2233 stat = (iwp_rx_phy_res_t *)sc->sc_rx_phy_res.buf;
2281 if ((len < 16) || (len > sc->sc_dmabuf_sz)) {
2296 sc->sc_rx_err++;
2304 sc->sc_assoc_id = *((uint16_t *)(wh + 1) + 2);
2307 sc->sc_assoc_id));
2327 sc->sc_rx_nobuf++;
2342 iwp_tx_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc)
2344 ieee80211com_t *ic = &sc->sc_ic;
2345 iwp_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3];
2361 sc->sc_tx_retries++;
2364 sc->sc_tx_retries));
2367 mutex_enter(&sc->sc_mt_lock);
2368 sc->sc_tx_timer = 0;
2369 mutex_exit(&sc->sc_mt_lock);
2371 mutex_enter(&sc->sc_tx_lock);
2378 if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count >> 3))) {
2379 sc->sc_need_reschedule = 0;
2380 mutex_exit(&sc->sc_tx_lock);
2382 mutex_enter(&sc->sc_tx_lock);
2385 mutex_exit(&sc->sc_tx_lock);
2392 iwp_cmd_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc)
2398 if (sc->sc_cmd_accum > 0) {
2399 sc->sc_cmd_accum--;
2403 mutex_enter(&sc->sc_glock);
2405 sc->sc_cmd_flag = SC_CMD_FLG_DONE;
2407 cv_signal(&sc->sc_cmd_cv);
2409 mutex_exit(&sc->sc_glock);
2421 iwp_ucode_alive(iwp_sc_t *sc, iwp_rx_desc_t *desc)
2427 struct iwp_calib_results *res_p = &sc->sc_calib_results;
2451 (void) memcpy(&sc->sc_card_alive_init, ar,
2457 mutex_enter(&sc->sc_glock);
2459 rv = iwp_alive_common(sc);
2463 mutex_exit(&sc->sc_glock);
2477 rv = iwp_cmd(sc, CALIBRATION_CFG_CMD, &cmd, sizeof (cmd), 1);
2481 mutex_exit(&sc->sc_glock);
2485 mutex_exit(&sc->sc_glock);
2492 (void) memcpy(&sc->sc_card_alive_run, ar,
2495 mutex_enter(&sc->sc_glock);
2500 rv = iwp_alive_common(sc);
2504 mutex_exit(&sc->sc_glock);
2512 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2518 mutex_exit(&sc->sc_glock);
2529 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2535 mutex_exit(&sc->sc_glock);
2546 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2553 mutex_exit(&sc->sc_glock);
2564 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
2571 mutex_exit(&sc->sc_glock);
2578 atomic_or_32(&sc->sc_flags, IWP_F_FW_INIT);
2579 cv_signal(&sc->sc_ucode_cv);
2581 mutex_exit(&sc->sc_glock);
2594 iwp_sc_t *sc;
2603 sc = (iwp_sc_t *)arg;
2604 ic = &sc->sc_ic;
2610 index = (sc->sc_shared->val0) & 0xfff;
2612 while (sc->sc_rxq.cur != index) {
2613 data = &sc->sc_rxq.data[sc->sc_rxq.cur];
2619 index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx,
2628 iwp_cmd_intr(sc, desc);
2633 iwp_rx_phy_intr(sc, desc);
2637 iwp_rx_mpdu_intr(sc, desc);
2641 iwp_tx_intr(sc, desc);
2645 iwp_ucode_alive(sc, desc);
2665 sc->sc_ostate = sc->sc_ic.ic_state;
2666 ieee80211_new_state(&sc->sc_ic,
2668 atomic_or_32(&sc->sc_flags,
2699 sc->sc_scan_pending++;
2712 iwp_save_calib_result(sc, desc);
2716 mutex_enter(&sc->sc_glock);
2717 atomic_or_32(&sc->sc_flags, IWP_F_FW_INIT);
2718 cv_signal(&sc->sc_ucode_cv);
2719 mutex_exit(&sc->sc_glock);
2740 sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % RX_QUEUE_SIZE;
2748 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7));
2753 IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2765 iwp_sc_t *sc;
2771 sc = (iwp_sc_t *)arg;
2773 r = IWP_READ(sc, CSR_INT);
2781 rfh = IWP_READ(sc, CSR_FH_INT_STATUS);
2789 IWP_WRITE(sc, CSR_INT_MASK, 0);
2794 IWP_WRITE(sc, CSR_INT, r);
2795 IWP_WRITE(sc, CSR_FH_INT_STATUS, rfh);
2800 iwp_stop(sc);
2801 sc->sc_ostate = sc->sc_ic.ic_state;
2804 if (!IWP_CHK_FAST_RECOVER(sc)) {
2805 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2808 atomic_or_32(&sc->sc_flags, IWP_F_HW_ERR_RECOVER);
2813 uint32_t tmp = IWP_READ(sc, CSR_GP_CNTRL);
2821 (void) ddi_intr_trigger_softint(sc->sc_soft_hdl, NULL);
2826 mutex_enter(&sc->sc_glock);
2827 atomic_or_32(&sc->sc_flags, IWP_F_PUT_SEG);
2828 cv_signal(&sc->sc_put_seg_cv);
2829 mutex_exit(&sc->sc_glock);
2842 IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2921 iwp_sc_t *sc;
2928 sc = (iwp_sc_t *)arg;
2929 ic = &sc->sc_ic;
2931 if (sc->sc_flags & IWP_F_SUSPEND) {
2941 if ((sc->sc_flags & IWP_F_HW_ERR_RECOVER) &&
2942 IWP_CHK_FAST_RECOVER(sc)) {
2968 iwp_sc_t *sc;
2986 sc = (iwp_sc_t *)ic;
2988 if (sc->sc_flags & IWP_F_SUSPEND) {
2997 mutex_enter(&sc->sc_tx_lock);
2998 ring = &sc->sc_txq[0];
3012 sc->sc_need_reschedule = 1;
3013 mutex_exit(&sc->sc_tx_lock);
3019 sc->sc_tx_nobuf++;
3026 mutex_exit(&sc->sc_tx_lock);
3036 mutex_enter(&sc->sc_tx_lock);
3038 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) {
3039 sc->sc_need_reschedule = 0;
3040 mutex_exit(&sc->sc_tx_lock);
3042 mutex_enter(&sc->sc_tx_lock);
3044 mutex_exit(&sc->sc_tx_lock);
3069 sc->sc_tx_err++;
3071 mutex_enter(&sc->sc_tx_lock);
3073 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) {
3074 sc->sc_need_reschedule = 0;
3075 mutex_exit(&sc->sc_tx_lock);
3077 mutex_enter(&sc->sc_tx_lock);
3079 mutex_exit(&sc->sc_tx_lock);
3113 sc->sc_tx_err++;
3115 mutex_enter(&sc->sc_tx_lock);
3117 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) {
3118 sc->sc_need_reschedule = 0;
3119 mutex_exit(&sc->sc_tx_lock);
3121 mutex_enter(&sc->sc_tx_lock);
3123 mutex_exit(&sc->sc_tx_lock);
3258 mutex_enter(&sc->sc_tx_lock);
3283 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3287 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3296 IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->desc_cur);
3298 mutex_exit(&sc->sc_tx_lock);
3309 mutex_enter(&sc->sc_mt_lock);
3310 if (0 == sc->sc_tx_timer) {
3311 sc->sc_tx_timer = 4;
3313 mutex_exit(&sc->sc_mt_lock);
3325 iwp_sc_t *sc;
3332 sc = (iwp_sc_t *)arg;
3333 ic = &sc->sc_ic;
3346 if (sc->sc_flags & IWP_F_RUNNING) {
3347 iwp_m_stop(sc);
3348 (void) iwp_m_start(sc);
3363 iwp_sc_t *sc;
3369 sc = (iwp_sc_t *)arg;
3371 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
3381 iwp_sc_t *sc;
3383 sc = (iwp_sc_t *)arg;
3384 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh);
3391 iwp_sc_t *sc;
3398 sc = (iwp_sc_t *)arg;
3399 ic = &sc->sc_ic;
3406 if (sc->sc_flags & IWP_F_RUNNING) {
3407 iwp_m_stop(sc);
3408 (void) iwp_m_start(sc);
3424 iwp_sc_t *sc;
3431 sc = (iwp_sc_t *)arg;
3432 ic = &sc->sc_ic;
3434 mutex_enter(&sc->sc_glock);
3444 *val = sc->sc_tx_nobuf;
3447 *val = sc->sc_rx_nobuf;
3450 *val = sc->sc_rx_err;
3466 *val = sc->sc_tx_err;
3469 *val = sc->sc_tx_retries;
3481 mutex_exit(&sc->sc_glock);
3484 mutex_exit(&sc->sc_glock);
3488 mutex_exit(&sc->sc_glock);
3500 iwp_sc_t *sc;
3507 sc = (iwp_sc_t *)arg;
3508 ic = &sc->sc_ic;
3510 err = iwp_init(sc);
3517 atomic_or_32(&sc->sc_flags, IWP_F_HW_ERR_RECOVER);
3523 atomic_or_32(&sc->sc_flags, IWP_F_RUNNING);
3534 iwp_sc_t *sc;
3540 sc = (iwp_sc_t *)arg;
3541 ic = &sc->sc_ic;
3543 iwp_stop(sc);
3548 iwp_release_calib_buffer(sc);
3552 atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER);
3553 atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL);
3555 atomic_and_32(&sc->sc_flags, ~IWP_F_RUNNING);
3556 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING);
3565 iwp_sc_t *sc;
3572 sc = (iwp_sc_t *)arg;
3573 ic = &sc->sc_ic;
3577 mutex_enter(&sc->sc_glock);
3578 err = iwp_config(sc);
3579 mutex_exit(&sc->sc_glock);
3611 iwp_thread(iwp_sc_t *sc)
3613 ieee80211com_t *ic = &sc->sc_ic;
3621 while (sc->sc_mf_thread_switch) {
3622 tmp = IWP_READ(sc, CSR_GP_CNTRL);
3624 atomic_and_32(&sc->sc_flags, ~IWP_F_RADIO_OFF);
3626 atomic_or_32(&sc->sc_flags, IWP_F_RADIO_OFF);
3632 if (sc->sc_flags & IWP_F_RADIO_OFF) {
3641 (sc->sc_flags & IWP_F_HW_ERR_RECOVER)) {
3646 iwp_stop(sc);
3648 if (IWP_CHK_FAST_RECOVER(sc)) {
3650 bcopy(&sc->sc_config, &sc->sc_config_save,
3651 sizeof (sc->sc_config));
3657 err = iwp_init(sc);
3667 atomic_or_32(&sc->sc_flags, IWP_F_RUNNING);
3671 if (!IWP_CHK_FAST_RECOVER(sc) ||
3672 iwp_fast_recover(sc) != IWP_SUCCESS) {
3673 atomic_and_32(&sc->sc_flags,
3677 if (sc->sc_ostate != IEEE80211_S_INIT) {
3685 (sc->sc_flags & IWP_F_SCANNING) && sc->sc_scan_pending) {
3689 sc->sc_scan_pending--;
3698 (sc->sc_flags & IWP_F_RATE_AUTO_CTL)) {
3700 if (clk > sc->sc_clk + drv_usectohz(1000000)) {
3701 iwp_amrr_timeout(sc);
3707 mutex_enter(&sc->sc_mt_lock);
3708 if (sc->sc_tx_timer) {
3711 sc->sc_tx_timer--;
3712 if (0 == sc->sc_tx_timer) {
3713 atomic_or_32(&sc->sc_flags,
3715 sc->sc_ostate = IEEE80211_S_RUN;
3723 mutex_exit(&sc->sc_mt_lock);
3726 mutex_enter(&sc->sc_mt_lock);
3727 sc->sc_mf_thread = NULL;
3728 cv_signal(&sc->sc_mt_cv);
3729 mutex_exit(&sc->sc_mt_lock);
3737 iwp_cmd(iwp_sc_t *sc, int code, const void *buf, int size, int async)
3739 iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM];
3744 ASSERT(mutex_owned(&sc->sc_glock));
3764 sc->sc_cmd_accum++;
3770 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3773 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3777 IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3785 while (sc->sc_cmd_flag != SC_CMD_FLG_DONE) {
3786 if (cv_timedwait(&sc->sc_cmd_cv,
3787 &sc->sc_glock, clk) < 0) {
3792 if (SC_CMD_FLG_DONE == sc->sc_cmd_flag) {
3793 sc->sc_cmd_flag = SC_CMD_FLG_NONE;
3796 sc->sc_cmd_flag = SC_CMD_FLG_NONE;
3806 iwp_set_led(iwp_sc_t *sc, uint8_t id, uint8_t off, uint8_t on)
3815 (void) iwp_cmd(sc, REPLY_LEDS_CMD, &led, sizeof (led), 1);
3822 iwp_hw_set_before_auth(iwp_sc_t *sc)
3824 ieee80211com_t *ic = &sc->sc_ic;
3832 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid);
3833 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, in->in_chan));
3835 sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0;
3836 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0;
3837 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0;
3840 sc->sc_config.cck_basic_rates = 0x03;
3841 sc->sc_config.ofdm_basic_rates = 0;
3844 sc->sc_config.cck_basic_rates = 0;
3845 sc->sc_config.ofdm_basic_rates = 0x15;
3847 sc->sc_config.cck_basic_rates = 0x0f;
3848 sc->sc_config.ofdm_basic_rates = 0xff;
3851 sc->sc_config.flags &= ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
3855 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_SLOT_MSK);
3857 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_SLOT_MSK);
3861 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
3863 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_PREAMBLE_MSK);
3870 LE_16(sc->sc_config.chan), LE_32(sc->sc_config.flags),
3871 LE_32(sc->sc_config.filter_flags),
3872 sc->sc_config.cck_basic_rates, sc->sc_config.ofdm_basic_rates,
3873 sc->sc_config.bssid[0], sc->sc_config.bssid[1],
3874 sc->sc_config.bssid[2], sc->sc_config.bssid[3],
3875 sc->sc_config.bssid[4], sc->sc_config.bssid[5]));
3877 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config,
3881 "failed to config chan%d\n", sc->sc_config.chan);
3888 err = iwp_add_ap_sta(sc);
3901 iwp_scan(iwp_sc_t *sc)
3903 ieee80211com_t *ic = &sc->sc_ic;
3904 iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM];
4067 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]
4070 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
4078 IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4087 iwp_config(iwp_sc_t *sc)
4089 ieee80211com_t *ic = &sc->sc_ic;
4102 err = iwp_cmd(sc, POWER_TABLE_CMD, &powertable,
4117 err = iwp_cmd(sc, REPLY_BT_CONFIG, &bt,
4128 (void) memset(&sc->sc_config, 0, sizeof (iwp_rxon_cmd_t));
4129 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr);
4130 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr);
4131 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan));
4132 sc->sc_config.flags = LE_32(RXON_FLG_BAND_24G_MSK);
4133 sc->sc_config.flags &= LE_32(~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4138 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS;
4139 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4145 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
4147 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
4148 sc->sc_config.filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4153 sc->sc_config.dev_type = RXON_DEV_TYPE_AP;
4156 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER;
4157 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
4165 sc->sc_config.cck_basic_rates = 0x0f;
4170 sc->sc_config.ofdm_basic_rates = 0xff;
4172 sc->sc_config.rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK |
4177 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config,
4192 err = iwp_cmd(sc, REPLY_REMOVE_STA, &rm_sta, sizeof (iwp_rem_sta_t), 0);
4208 err = iwp_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 0);
4229 iwp_sc_t *sc;
4231 sc = ddi_get_soft_state(iwp_soft_state_p, ddi_get_instance(dip));
4232 if (NULL == sc) {
4245 atomic_or_32(&sc->sc_flags, IWP_F_QUIESCED);
4250 iwp_stop(sc);
4256 iwp_stop_master(iwp_sc_t *sc)
4261 tmp = IWP_READ(sc, CSR_RESET);
4262 IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER);
4264 tmp = IWP_READ(sc, CSR_GP_CNTRL);
4271 if (IWP_READ(sc, CSR_RESET) &
4287 iwp_power_up(iwp_sc_t *sc)
4291 iwp_mac_access_enter(sc);
4292 tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL);
4295 iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4296 iwp_mac_access_exit(sc);
4306 iwp_preinit(iwp_sc_t *sc)
4316 IWP_WRITE(sc, CSR_INT, 0xffffffff);
4318 tmp = IWP_READ(sc, CSR_GIO_CHICKEN_BITS);
4319 IWP_WRITE(sc, CSR_GIO_CHICKEN_BITS,
4322 tmp = IWP_READ(sc, CSR_GP_CNTRL);
4323 IWP_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4329 if (IWP_READ(sc, CSR_GP_CNTRL) &
4340 iwp_mac_access_enter(sc);
4342 iwp_reg_write(sc, ALM_APMG_CLK_EN, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4345 tmp = iwp_reg_read(sc, ALM_APMG_PCIDEV_STT);
4346 iwp_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp |
4348 iwp_mac_access_exit(sc);
4350 radio_cfg = IWP_READ_EEP_SHORT(sc, EEP_SP_RADIO_CONFIGURATION);
4352 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG);
4353 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4364 IWP_WRITE(sc, CSR_INT_COALESCING, 512 / 32);
4366 (void) iwp_power_up(sc);
4368 if ((sc->sc_rev & 0x80) == 0x80 && (sc->sc_rev & 0x7f) < 8) {
4369 tmp = ddi_get32(sc->sc_cfg_handle,
4370 (uint32_t *)(sc->sc_cfg_base + 0xe8));
4371 ddi_put32(sc->sc_cfg_handle,
4372 (uint32_t *)(sc->sc_cfg_base + 0xe8),
4376 vlink = ddi_get8(sc->sc_cfg_handle,
4377 (uint8_t *)(sc->sc_cfg_base + 0xf0));
4378 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0),
4381 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG);
4384 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, tmp);
4389 iwp_mac_access_enter(sc);
4390 tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL);
4392 iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4395 tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL);
4397 iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4398 iwp_mac_access_exit(sc);
4400 if (PA_TYPE_MIX == sc->sc_chip_param.pa_type) {
4401 IWP_WRITE(sc, CSR_GP_DRIVER_REG,
4405 if (PA_TYPE_INTER == sc->sc_chip_param.pa_type) {
4407 IWP_WRITE(sc, CSR_GP_DRIVER_REG,
4418 iwp_eep_sem_down(iwp_sc_t *sc)
4424 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG);
4425 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4429 if (IWP_READ(sc, CSR_HW_IF_CONFIG_REG) &
4443 iwp_eep_sem_up(iwp_sc_t *sc)
4447 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG);
4448 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4456 iwp_eep_load(iwp_sc_t *sc)
4460 uint16_t addr, eep_sz = sizeof (sc->sc_eep_map);
4461 uint16_t *eep_p = (uint16_t *)&sc->sc_eep_map;
4466 eep_gp = IWP_READ(sc, CSR_EEPROM_GP);
4474 rr = iwp_eep_sem_down(sc);
4482 IWP_WRITE(sc, CSR_EEPROM_REG, addr<<1);
4483 tmp = IWP_READ(sc, CSR_EEPROM_REG);
4484 IWP_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2));
4487 rv = IWP_READ(sc, CSR_EEPROM_REG);
4497 iwp_eep_sem_up(sc);
4504 iwp_eep_sem_up(sc);
4512 iwp_get_mac_from_eep(iwp_sc_t *sc)
4514 ieee80211com_t *ic = &sc->sc_ic;
4516 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->sc_eep_map[EEP_MAC_ADDRESS]);
4528 iwp_init(iwp_sc_t *sc)
4536 iwp_release_calib_buffer(sc);
4538 mutex_enter(&sc->sc_glock);
4539 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT);
4541 err = iwp_init_common(sc);
4543 mutex_exit(&sc->sc_glock);
4550 (void) memcpy(sc->sc_dma_fw_data_bak.mem_va,
4551 sc->sc_dma_fw_data.mem_va,
4552 sc->sc_dma_fw_data.alength);
4555 err = iwp_load_init_firmware(sc);
4559 mutex_exit(&sc->sc_glock);
4566 IWP_WRITE(sc, CSR_RESET, 0);
4569 while (!(sc->sc_flags & IWP_F_FW_INIT)) {
4570 if (cv_timedwait(&sc->sc_ucode_cv,
4571 &sc->sc_glock, clk) < 0) {
4576 if (!(sc->sc_flags & IWP_F_FW_INIT)) {
4579 mutex_exit(&sc->sc_glock);
4583 mutex_exit(&sc->sc_glock);
4588 iwp_stop(sc);
4590 mutex_enter(&sc->sc_glock);
4591 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT);
4593 err = iwp_init_common(sc);
4595 mutex_exit(&sc->sc_glock);
4602 err = iwp_load_run_firmware(sc);
4606 mutex_exit(&sc->sc_glock);
4613 IWP_WRITE(sc, CSR_RESET, 0);
4616 while (!(sc->sc_flags & IWP_F_FW_INIT)) {
4617 if (cv_timedwait(&sc->sc_ucode_cv,
4618 &sc->sc_glock, clk) < 0) {
4623 if (!(sc->sc_flags & IWP_F_FW_INIT)) {
4626 mutex_exit(&sc->sc_glock);
4630 mutex_exit(&sc->sc_glock);
4634 mutex_enter(&sc->sc_glock);
4635 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT);
4641 err = iwp_config(sc);
4645 mutex_exit(&sc->sc_glock);
4652 mutex_exit(&sc->sc_glock);
4660 iwp_stop(iwp_sc_t *sc)
4666 if (!(sc->sc_flags & IWP_F_QUIESCED)) {
4667 mutex_enter(&sc->sc_glock);
4670 IWP_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4674 IWP_WRITE(sc, CSR_INT_MASK, 0);
4675 IWP_WRITE(sc, CSR_INT, CSR_INI_SET_MASK);
4676 IWP_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff);
4682 iwp_reset_tx_ring(sc, &sc->sc_txq[i]);
4688 iwp_reset_rx_ring(sc);
4690 iwp_mac_access_enter(sc);
4691 iwp_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4692 iwp_mac_access_exit(sc);
4696 iwp_stop_master(sc);
4698 mutex_enter(&sc->sc_mt_lock);
4699 sc->sc_tx_timer = 0;
4700 mutex_exit(&sc->sc_mt_lock);
4702 tmp = IWP_READ(sc, CSR_RESET);
4703 IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET);
4706 if (!(sc->sc_flags & IWP_F_QUIESCED)) {
4707 mutex_exit(&sc->sc_glock);
4750 iwp_amrr_timeout(iwp_sc_t *sc)
4752 ieee80211com_t *ic = &sc->sc_ic;
4763 sc->sc_clk = ddi_get_lbolt();
4825 iwp_eep_addr_trans(iwp_sc_t *sc, uint32_t indi_addr)
4832 return (&sc->sc_eep_map[di_addr]);
4837 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_GENERAL);
4840 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_HOST);
4843 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_REGULATORY);
4846 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_CALIBRATION);
4849 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_PROCESS_ADJST);
4852 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_OTHERS);
4863 return (&sc->sc_eep_map[di_addr]);
4870 iwp_put_seg_fw(iwp_sc_t *sc, uint32_t addr_s, uint32_t addr_d, uint32_t len)
4873 iwp_mac_access_enter(sc);
4875 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL),
4878 IWP_WRITE(sc, IWP_FH_SRVC_CHNL_SRAM_ADDR_REG(IWP_FH_SRVC_CHNL), addr_d);
4880 IWP_WRITE(sc, IWP_FH_TFDIB_CTRL0_REG(IWP_FH_SRVC_CHNL),
4883 IWP_WRITE(sc, IWP_FH_TFDIB_CTRL1_REG(IWP_FH_SRVC_CHNL), len);
4885 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_BUF_STS_REG(IWP_FH_SRVC_CHNL),
4890 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL),
4895 iwp_mac_access_exit(sc);
4904 iwp_alive_common(iwp_sc_t *sc)
4915 iwp_mac_access_enter(sc);
4920 sc->sc_scd_base = iwp_reg_read(sc, IWP_SCD_SRAM_BASE_ADDR);
4922 for (base = sc->sc_scd_base + IWP_SCD_CONTEXT_DATA_OFFSET;
4923 base < sc->sc_scd_base + IWP_SCD_TX_STTS_BITMAP_OFFSET;
4925 iwp_mem_write(sc, base, 0);
4928 for (; base < sc->sc_scd_base + IWP_SCD_TRANSLATE_TBL_OFFSET;
4930 iwp_mem_write(sc, base, 0);
4934 iwp_mem_write(sc, base + i, 0);
4937 iwp_reg_write(sc, IWP_SCD_DRAM_BASE_ADDR,
4938 sc->sc_dma_sh.cookie.dmac_address >> 10);
4940 iwp_reg_write(sc, IWP_SCD_QUEUECHAIN_SEL,
4943 iwp_reg_write(sc, IWP_SCD_AGGR_SEL, 0);
4946 iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(i), 0);
4947 IWP_WRITE(sc, HBUS_TARG_WRPTR, 0 | (i << 8));
4948 iwp_mem_write(sc, sc->sc_scd_base +
4950 iwp_mem_write(sc, sc->sc_scd_base +
4960 iwp_reg_write(sc, IWP_SCD_INTERRUPT_MASK, (1 << IWP_NUM_QUEUES) - 1);
4962 iwp_reg_write(sc, (IWP_SCD_BASE + 0x10),
4965 IWP_WRITE(sc, HBUS_TARG_WRPTR, (IWP_CMD_QUEUE_NUM << 8));
4966 iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(IWP_CMD_QUEUE_NUM), 0);
4973 iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i),
4980 iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(IWP_CMD_QUEUE_NUM),
4987 iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i),
4994 iwp_mac_access_exit(sc);
4998 rv = iwp_cmd(sc, COEX_PRIORITY_TABLE_CMD, &w_cmd, sizeof (w_cmd), 1);
5008 c_cmd.data.cap_pin1 = LE_16(sc->sc_eep_calib->xtal_calib[0]);
5009 c_cmd.data.cap_pin2 = LE_16(sc->sc_eep_calib->xtal_calib[1]);
5011 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, &c_cmd, sizeof (c_cmd), 1);
5031 iwp_save_calib_result(iwp_sc_t *sc, iwp_rx_desc_t *desc)
5033 struct iwp_calib_results *res_p = &sc->sc_calib_results;
5106 iwp_release_calib_buffer(iwp_sc_t *sc)
5108 if (sc->sc_calib_results.lo_res != NULL) {
5109 kmem_free(sc->sc_calib_results.lo_res,
5110 sc->sc_calib_results.lo_res_len);
5111 sc->sc_calib_results.lo_res = NULL;
5114 if (sc->sc_calib_results.tx_iq_res != NULL) {
5115 kmem_free(sc->sc_calib_results.tx_iq_res,
5116 sc->sc_calib_results.tx_iq_res_len);
5117 sc->sc_calib_results.tx_iq_res = NULL;
5120 if (sc->sc_calib_results.tx_iq_perd_res != NULL) {
5121 kmem_free(sc->sc_calib_results.tx_iq_perd_res,
5122 sc->sc_calib_results.tx_iq_perd_res_len);
5123 sc->sc_calib_results.tx_iq_perd_res = NULL;
5126 if (sc->sc_calib_results.base_band_res != NULL) {
5127 kmem_free(sc->sc_calib_results.base_band_res,
5128 sc->sc_calib_results.base_band_res_len);
5129 sc->sc_calib_results.base_band_res = NULL;
5138 iwp_init_common(iwp_sc_t *sc)
5143 (void) iwp_preinit(sc);
5145 tmp = IWP_READ(sc, CSR_GP_CNTRL);
5155 iwp_mac_access_enter(sc);
5156 IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
5158 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
5159 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
5160 sc->sc_rxq.dma_desc.cookie.dmac_address >> 8);
5162 IWP_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG,
5163 ((uint32_t)(sc->sc_dma_sh.cookie.dmac_address +
5166 IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG,
5172 iwp_mac_access_exit(sc);
5173 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG,
5179 iwp_mac_access_enter(sc);
5180 iwp_reg_write(sc, IWP_SCD_TXFACT, 0);
5185 IWP_WRITE(sc, IWP_FH_KW_MEM_ADDR_REG,
5186 sc->sc_dma_kw.cookie.dmac_address >> 4);
5189 IWP_WRITE(sc, FH_MEM_CBBC_QUEUE(qid),
5190 sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8);
5191 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(qid),
5196 iwp_mac_access_exit(sc);
5201 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5202 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR,
5208 IWP_WRITE(sc, CSR_INT, 0xffffffff);
5213 IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
5215 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5216 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5222 iwp_fast_recover(iwp_sc_t *sc)
5224 ieee80211com_t *ic = &sc->sc_ic;
5227 mutex_enter(&sc->sc_glock);
5230 bcopy(&sc->sc_config_save, &sc->sc_config,
5231 sizeof (sc->sc_config));
5233 sc->sc_config.assoc_id = 0;
5234 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
5236 if ((err = iwp_hw_set_before_auth(sc)) != IWP_SUCCESS) {
5239 mutex_exit(&sc->sc_glock);
5243 bcopy(&sc->sc_config_save, &sc->sc_config,
5244 sizeof (sc->sc_config));
5247 err = iwp_run_state_config(sc);
5251 mutex_exit(&sc->sc_glock);
5255 iwp_set_led(sc, 2, 0, 1);
5257 mutex_exit(&sc->sc_glock);
5259 atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER);
5270 iwp_run_state_config(iwp_sc_t *sc)
5272 struct ieee80211com *ic = &sc->sc_ic;
5279 sc->sc_config.assoc_id = in->in_associd & 0x3fff;
5285 sc->sc_config.flags &=
5290 sc->sc_config.flags |=
5295 sc->sc_config.flags |=
5299 sc->sc_config.filter_flags |=
5303 sc->sc_config.filter_flags |=
5310 sc->sc_config.chan, sc->sc_config.flags,
5311 sc->sc_config.filter_flags));
5313 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config,
5329 iwp_overwrite_ic_default(iwp_sc_t *sc)
5331 ieee80211com_t *ic = &sc->sc_ic;
5333 sc->sc_newstate = ic->ic_newstate;
5344 iwp_add_ap_sta(iwp_sc_t *sc)
5346 ieee80211com_t *ic = &sc->sc_ic;
5359 err = iwp_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
5373 iwp_eep_ver_chk(iwp_sc_t *sc)
5375 if ((IWP_READ_EEP_SHORT(sc, EEP_VERSION) < 0x011a) ||
5376 (sc->sc_eep_calib->tx_pow_calib_hdr.calib_version < 4)) {
5389 iwp_set_chip_param(iwp_sc_t *sc)
5391 if ((0x008d == sc->sc_dev_id) ||
5392 (0x008e == sc->sc_dev_id)) {
5393 sc->sc_chip_param.phy_mode = PHY_MODE_G |
5396 sc->sc_chip_param.tx_ant = ANT_A | ANT_B;
5397 sc->sc_chip_param.rx_ant = ANT_A | ANT_B;
5399 sc->sc_chip_param.pa_type = PA_TYPE_MIX;
5402 if ((0x422c == sc->sc_dev_id) ||
5403 (0x4239 == sc->sc_dev_id)) {
5404 sc->sc_chip_param.phy_mode = PHY_MODE_G |
5407 sc->sc_chip_param.tx_ant = ANT_B | ANT_C;
5408 sc->sc_chip_param.rx_ant = ANT_B | ANT_C;
5410 sc->sc_chip_param.pa_type = PA_TYPE_INTER;
5413 if ((0x422b == sc->sc_dev_id) ||
5414 (0x4238 == sc->sc_dev_id)) {
5415 sc->sc_chip_param.phy_mode = PHY_MODE_G |
5418 sc->sc_chip_param.tx_ant = ANT_A | ANT_B | ANT_C;
5419 sc->sc_chip_param.rx_ant = ANT_A | ANT_B | ANT_C;
5421 sc->sc_chip_param.pa_type = PA_TYPE_SYSTEM;