Lines Matching +defs:val +defs:channel
253 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
356 * Rx Config Reg for channel 0 (only channel used)
366 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
403 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG),
404 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
424 * To use a Tx DMA channel, driver must initialize its
433 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
453 * After stopping Tx DMA channel (writing 0 to
455 * IWK_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
456 * (channel's buffers empty | no pending requests).
459 * 31-24: 1 = Channel buffers empty (channel 7:0)
460 * 23-16: 1 = No pending requests (channel 7:0)
592 * RCSR: channel 0 rx_config register defines
609 * RCSR: channel 1 rx_config register defines
628 * RCSR channel 0 config register values
634 * RCSR channel 1 config register values
684 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
685 * but one DMA channel may take input from several queues.
688 * BMC TODO: CONFIRM channel assignments, esp for 0/1
808 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7
867 * Sets up queue mode and assigns queue to Tx DMA channel.
1136 #define BIT_FH_INT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */
1137 #define BIT_FH_INT_RX_CHNL1 (1<<17) /* Rx channel 1 */
1138 #define BIT_FH_INT_RX_CHNL0 (1<<16) /* Rx channel 0 */
1139 #define BIT_FH_INT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */
1140 #define BIT_FH_INT_TX_CHNL1 (1<<1) /* Tx channel 1 */
1141 #define BIT_FH_INT_TX_CHNL0 (1<<0) /* Tx channel 0 */
1278 * spectrum and channel data structures
1544 * 1) Regulatory information (max txpower and channel usage flags) is provided
1545 * separately for each channel that can possibly supported by 4965.
1576 * To calculate a txpower setting for a given desired target txpower, channel,
1580 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
1607 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
1608 * widths and 40 Mhz (.11n fat) channel widths; there is no separate
1615 * 3) Determine (EEPROM) calibration subband for the target channel, by
1623 * Interpolation is based on difference between target channel's frequency
1624 * and the sample channels' frequencies. Since channel numbers are based
1625 * on frequency (5 MHz between each channel number), this is equivalent
1626 * to interpolating based on channel number differences.
1629 * edges of the subband. The target channel may be "outside" of the
1647 * If the target channel happens to be one of the sample channels, the
1648 * results should agree with the sample channel's measurements!
1699 * NOTE: Voltage compensation is independent of band/channel.
1710 * values in "initialize alive", one pair for each of 5 channel ranges:
1712 * Group 0: 5 GHz channel 34-43
1713 * Group 1: 5 GHz channel 44-70
1714 * Group 2: 5 GHz channel 71-124
1715 * Group 3: 5 GHz channel 125-200
1720 * so as to reduce gain (if necessary) of the "hotter" channel. This
1830 * power varies with temperature, voltage, and channel frequency, and also
2087 * and channel-specific; each channel has an individual regulatory limit
2170 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
2238 uint16_t channel;
2245 uint16_t channel;
2254 uint16_t channel;
2399 uint16_t channel; /* channel number */
2433 uint16_t val;
2743 uint32_t therm_r1[2]; /* signed 1st for normal, 2nd for FAT channel */
3196 #define IWK_WRITE(sc, reg, val) \
3197 ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val))