Lines Matching defs:CSR_BASE
1007 #define CSR_BASE (0x0)
1015 #define CSR_SW_VER (CSR_BASE+0x000)
1016 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
1017 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
1018 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
1019 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
1020 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */
1021 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
1022 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */
1023 #define CSR_GP_CNTRL (CSR_BASE+0x024)
1025 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
1026 #define CSR_EEPROM_GP (CSR_BASE+0x030)
1027 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
1028 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
1029 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
1030 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
1031 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
1032 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
1033 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
1038 #define BSM_BASE (CSR_BASE + 0x3400)
1057 #define BSM_SRAM_LOWER_BOUND (CSR_BASE + 0x3800)