Lines Matching +defs:val +defs:channel
255 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
357 * Rx Config Reg for channel 0 (only channel used)
367 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
404 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG),
405 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
425 * To use a Tx DMA channel, driver must initialize its
431 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
444 * After stopping Tx DMA channel (writing 0 to
445 * IWH_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
446 * (channel's buffers empty | no pending requests).
449 * 31-24: 1 = Channel buffers empty (channel 7:0)
450 * 23-16: 1 = No pending requests (channel 7:0)
590 * RCSR: channel 0 rx_config register defines
607 * RCSR: channel 1 rx_config register defines
632 * RCSR channel 0 config register values
638 * RCSR channel 1 config register values
688 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
689 * but one DMA channel may take input from several queues.
692 * BMC TODO: CONFIRM channel assignments, esp for 0/1
1091 #define BIT_FH_INT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */
1092 #define BIT_FH_INT_RX_CHNL1 (1<<17) /* Rx channel 1 */
1093 #define BIT_FH_INT_RX_CHNL0 (1<<16) /* Rx channel 0 */
1094 #define BIT_FH_INT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */
1095 #define BIT_FH_INT_TX_CHNL1 (1<<1) /* Tx channel 1 */
1096 #define BIT_FH_INT_TX_CHNL0 (1<<0) /* Tx channel 0 */
1223 * spectrum and channel data structures
1489 uint8_t channel;
1504 * legacy mode(no FAT channel, no MIMO, no short guard interval).
1507 * d) After trying 2 HT rates, switch to legacy mode(no FAT channel,
1630 uint16_t channel; /* channel number */
1675 uint16_t val;
1998 uint32_t therm_r1[2]; /* signed 1st for normal, 2nd for FAT channel */
2573 #define IWH_WRITE(sc, reg, val) \
2574 ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val))