Lines Matching defs:hw
33 e1000_pci_set_mwi(struct e1000_hw *hw)
35 uint16_t val = hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE;
37 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val);
41 e1000_pci_clear_mwi(struct e1000_hw *hw)
43 uint16_t val = hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE;
45 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val);
49 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
51 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value);
55 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
58 pci_config_get16(OS_DEP(hw)->cfg_handle, reg);
67 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
74 status = pci_lcap_locate((OS_DEP(hw))->cfg_handle, pcie_id, &pcie_cap);
78 *value = pci_config_get16(OS_DEP(hw)->cfg_handle,
91 e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
98 status = pci_lcap_locate(OS_DEP(hw)->cfg_handle, pcie_id, &pcie_cap);
102 pci_config_put16(OS_DEP(hw)->cfg_handle,
113 e1000_rar_clear(struct e1000_hw *hw, uint32_t index)
121 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
122 E1000_WRITE_FLUSH(hw);
129 e1000_rar_set_vmdq(struct e1000_hw *hw, const uint8_t *addr, uint32_t index,
162 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
163 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
164 E1000_WRITE_FLUSH(hw);