Lines Matching defs:igb
38 igb_t *igb = (igb_t *)arg;
39 struct e1000_hw *hw = &igb->hw;
43 igb_ks = (igb_stat_t *)igb->igb_ks->ks_data;
45 mutex_enter(&igb->gen_lock);
47 if (igb->igb_state & IGB_SUSPENDED) {
48 mutex_exit(&igb->gen_lock);
54 *val = igb->link_speed * 1000000ull;
58 igb->stat_mprc += E1000_READ_REG(hw, E1000_MPRC);
59 *val = igb->stat_mprc;
63 igb->stat_bprc += E1000_READ_REG(hw, E1000_BPRC);
64 *val = igb->stat_bprc;
68 igb->stat_mptc += E1000_READ_REG(hw, E1000_MPTC);
69 *val = igb->stat_mptc;
73 igb->stat_bptc += E1000_READ_REG(hw, E1000_BPTC);
74 *val = igb->stat_bptc;
78 igb->stat_rnbc += E1000_READ_REG(hw, E1000_RNBC);
79 *val = igb->stat_rnbc;
83 igb->stat_rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
84 igb->stat_algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
87 igb->stat_crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
88 igb->stat_cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
89 *val = igb->stat_rxerrc +
90 igb->stat_algnerrc +
92 igb->stat_crcerrs +
93 igb->stat_cexterr;
101 igb->stat_ecol += E1000_READ_REG(hw, E1000_ECOL);
102 *val = igb->stat_ecol;
106 igb->stat_colc += E1000_READ_REG(hw, E1000_COLC);
107 *val = igb->stat_colc;
118 igb->stat_tor += (uint64_t)high_val << 32 | (uint64_t)low_val;
119 *val = igb->stat_tor;
123 igb->stat_tpr += E1000_READ_REG(hw, E1000_TPR);
124 *val = igb->stat_tpr;
135 igb->stat_tot += (uint64_t)high_val << 32 | (uint64_t)low_val;
136 *val = igb->stat_tot;
140 igb->stat_tpt += E1000_READ_REG(hw, E1000_TPT);
141 *val = igb->stat_tpt;
146 igb->stat_algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
147 *val = igb->stat_algnerrc;
151 igb->stat_crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
152 *val = igb->stat_crcerrs;
156 igb->stat_scc += E1000_READ_REG(hw, E1000_SCC);
157 *val = igb->stat_scc;
161 igb->stat_mcc += E1000_READ_REG(hw, E1000_MCC);
162 *val = igb->stat_mcc;
166 igb->stat_sec += E1000_READ_REG(hw, E1000_SEC);
167 *val = igb->stat_sec;
171 igb->stat_dc += E1000_READ_REG(hw, E1000_DC);
172 *val = igb->stat_dc;
176 igb->stat_latecol += E1000_READ_REG(hw, E1000_LATECOL);
177 *val = igb->stat_latecol;
181 igb->stat_ecol += E1000_READ_REG(hw, E1000_ECOL);
182 *val = igb->stat_ecol;
186 igb->stat_ecol += E1000_READ_REG(hw, E1000_ECOL);
187 *val = igb->stat_ecol;
191 igb->stat_cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
192 *val = igb->stat_cexterr;
196 igb->stat_roc += E1000_READ_REG(hw, E1000_ROC);
197 *val = igb->stat_roc;
201 igb->stat_rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
202 *val = igb->stat_rxerrc;
216 switch (igb->link_speed) {
225 (igb->param_100t4_cap == 1) ?
238 *val = igb->param_1000fdx_cap;
242 *val = igb->param_1000hdx_cap;
246 *val = igb->param_100fdx_cap;
250 *val = igb->param_100hdx_cap;
254 *val = igb->param_10fdx_cap;
258 *val = igb->param_10hdx_cap;
262 *val = igb->param_asym_pause_cap;
266 *val = igb->param_pause_cap;
270 *val = igb->param_autoneg_cap;
274 *val = igb->param_adv_1000fdx_cap;
278 *val = igb->param_adv_1000hdx_cap;
282 *val = igb->param_adv_100fdx_cap;
286 *val = igb->param_adv_100hdx_cap;
290 *val = igb->param_adv_10fdx_cap;
294 *val = igb->param_adv_10hdx_cap;
298 *val = igb->param_adv_asym_pause_cap;
302 *val = igb->param_adv_pause_cap;
310 *val = igb->param_lp_1000fdx_cap;
314 *val = igb->param_lp_1000hdx_cap;
318 *val = igb->param_lp_100fdx_cap;
322 *val = igb->param_lp_100hdx_cap;
326 *val = igb->param_lp_10fdx_cap;
330 *val = igb->param_lp_10hdx_cap;
334 *val = igb->param_lp_asym_pause_cap;
338 *val = igb->param_lp_pause_cap;
342 *val = igb->param_lp_autoneg_cap;
346 *val = igb->param_asym_pause_cap;
350 *val = igb->param_pause_cap;
358 *val = (igb->link_duplex == FULL_DUPLEX) ?
363 igb->stat_ruc += E1000_READ_REG(hw, E1000_RUC);
364 *val = igb->stat_ruc;
368 *val = igb->param_rem_fault;
372 *val = igb->param_adv_rem_fault;
376 *val = igb->param_lp_rem_fault;
380 igb->stat_rjc += E1000_READ_REG(hw, E1000_RJC);
381 *val = igb->stat_rjc;
385 *val = igb->param_100t4_cap;
389 *val = igb->param_adv_100t4_cap;
393 *val = igb->param_lp_100t4_cap;
397 mutex_exit(&igb->gen_lock);
401 mutex_exit(&igb->gen_lock);
403 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
404 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
418 igb_t *igb = (igb_t *)arg;
420 mutex_enter(&igb->gen_lock);
422 if (igb->igb_state & IGB_SUSPENDED) {
423 mutex_exit(&igb->gen_lock);
427 if (igb_start(igb, B_TRUE) != IGB_SUCCESS) {
428 mutex_exit(&igb->gen_lock);
432 atomic_or_32(&igb->igb_state, IGB_STARTED);
434 mutex_exit(&igb->gen_lock);
439 igb_enable_watchdog_timer(igb);
451 igb_t *igb = (igb_t *)arg;
453 mutex_enter(&igb->gen_lock);
455 if (igb->igb_state & IGB_SUSPENDED) {
456 mutex_exit(&igb->gen_lock);
460 atomic_and_32(&igb->igb_state, ~IGB_STARTED);
462 igb_stop(igb, B_TRUE);
464 mutex_exit(&igb->gen_lock);
469 igb_disable_watchdog_timer(igb);
478 igb_t *igb = (igb_t *)arg;
481 mutex_enter(&igb->gen_lock);
483 if (igb->igb_state & IGB_SUSPENDED) {
484 mutex_exit(&igb->gen_lock);
488 reg_val = E1000_READ_REG(&igb->hw, E1000_RCTL);
495 E1000_WRITE_REG(&igb->hw, E1000_RCTL, reg_val);
497 mutex_exit(&igb->gen_lock);
499 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
500 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
514 igb_t *igb = (igb_t *)arg;
517 mutex_enter(&igb->gen_lock);
519 if (igb->igb_state & IGB_SUSPENDED) {
520 mutex_exit(&igb->gen_lock);
524 result = (add) ? igb_multicst_add(igb, mcst_addr)
525 : igb_multicst_remove(igb, mcst_addr);
527 mutex_exit(&igb->gen_lock);
539 igb_t *igb = (igb_t *)arg;
546 mutex_enter(&igb->gen_lock);
547 if (igb->igb_state & IGB_SUSPENDED) {
548 mutex_exit(&igb->gen_lock);
552 mutex_exit(&igb->gen_lock);
559 status = igb_loopback_ioctl(igb, iocp, mp);
611 igb_t *igb = rx_group->igb;
612 struct e1000_hw *hw = &igb->hw;
615 mutex_enter(&igb->gen_lock);
617 if (igb->igb_state & IGB_SUSPENDED) {
618 mutex_exit(&igb->gen_lock);
622 if (igb->unicst_avail == 0) {
624 mutex_exit(&igb->gen_lock);
629 * The slots from 0 to igb->num_rx_groups are reserved slots which
635 if (igb->unicst_addr[rx_group->index].mac.set == 1) {
640 for (i = igb->num_rx_groups; i < igb->unicst_total; i++) {
641 if (igb->unicst_addr[i].mac.set == 0) {
651 mutex_exit(&igb->gen_lock);
656 e1000_rar_set_vmdq(hw, mac_addr, slot, igb->vmdq_mode, rx_group->index);
658 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL);
659 igb->unicst_addr[slot].mac.group_index = rx_group->index;
660 igb->unicst_addr[slot].mac.set = 1;
661 igb->unicst_avail--;
663 mutex_exit(&igb->gen_lock);
675 igb_t *igb = rx_group->igb;
676 struct e1000_hw *hw = &igb->hw;
679 mutex_enter(&igb->gen_lock);
681 if (igb->igb_state & IGB_SUSPENDED) {
682 mutex_exit(&igb->gen_lock);
686 slot = igb_unicst_find(igb, mac_addr);
688 mutex_exit(&igb->gen_lock);
692 if (igb->unicst_addr[slot].mac.set == 0) {
693 mutex_exit(&igb->gen_lock);
699 igb->unicst_addr[slot].mac.set = 0;
700 igb->unicst_avail++;
702 mutex_exit(&igb->gen_lock);
714 igb_t *igb = rx_ring->igb;
715 struct e1000_hw *hw = &igb->hw;
718 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
720 igb->eims_mask |= (E1000_EICR_RX_QUEUE0 << index);
721 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
722 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
726 igb->ims_mask |= E1000_IMS_RXT0;
727 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
742 igb_t *igb = rx_ring->igb;
743 struct e1000_hw *hw = &igb->hw;
746 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
748 igb->eims_mask &= ~(E1000_EICR_RX_QUEUE0 << index);
751 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
755 igb->ims_mask &= ~E1000_IMS_RXT0;
768 igb_get_rx_ring_index(igb_t *igb, int gindex, int rindex)
773 for (i = 0; i < igb->num_rx_rings; i++) {
774 rx_ring = &igb->rx_rings[i];
803 igb_t *igb = (igb_t *)arg;
815 global_index = igb_get_rx_ring_index(igb, rg_index, index);
819 rx_ring = &igb->rx_rings[global_index];
831 if (igb->intr_type & (DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI)) {
833 igb->htable[rx_ring->intr_vector];
838 ASSERT(index < igb->num_tx_rings);
840 igb_tx_ring_t *tx_ring = &igb->tx_rings[index];
848 if (igb->intr_type & (DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI)) {
850 igb->htable[tx_ring->intr_vector];
863 igb_t *igb = (igb_t *)arg;
869 ASSERT((index >= 0) && (index < igb->num_rx_groups));
871 rx_group = &igb->rx_groups[index];
879 infop->mgi_count = (igb->num_rx_rings / igb->num_rx_groups);
897 igb_t *igb = (igb_t *)arg;
909 if (!igb->tx_hcksum_enable)
918 if (igb->lso_enable) {
932 cap_rings->mr_rnum = igb->num_rx_rings;
933 cap_rings->mr_gnum = igb->num_rx_groups;
942 cap_rings->mr_rnum = igb->num_tx_rings;
964 igb_t *igb = (igb_t *)arg;
965 struct e1000_hw *hw = &igb->hw;
972 mutex_enter(&igb->gen_lock);
973 if (igb->igb_state & IGB_SUSPENDED) {
974 mutex_exit(&igb->gen_lock);
978 if (igb->loopback_mode != IGB_LB_NONE && igb_param_locked(pr_num)) {
983 mutex_exit(&igb->gen_lock);
994 igb->param_en_1000fdx_cap = *(uint8_t *)pr_val;
995 igb->param_adv_1000fdx_cap = *(uint8_t *)pr_val;
1002 igb->param_en_100fdx_cap = *(uint8_t *)pr_val;
1003 igb->param_adv_100fdx_cap = *(uint8_t *)pr_val;
1010 igb->param_en_100hdx_cap = *(uint8_t *)pr_val;
1011 igb->param_adv_100hdx_cap = *(uint8_t *)pr_val;
1018 igb->param_en_10fdx_cap = *(uint8_t *)pr_val;
1019 igb->param_adv_10fdx_cap = *(uint8_t *)pr_val;
1026 igb->param_en_10hdx_cap = *(uint8_t *)pr_val;
1027 igb->param_adv_10hdx_cap = *(uint8_t *)pr_val;
1034 igb->param_adv_autoneg_cap = *(uint8_t *)pr_val;
1058 if (igb_setup_link(igb, B_TRUE) != IGB_SUCCESS)
1078 if (igb->igb_state & IGB_STARTED) {
1083 cur_mtu = igb->default_mtu;
1095 err = mac_maxsdu_update(igb->mac_hdl, new_mtu);
1097 igb->default_mtu = new_mtu;
1098 igb->max_frame_size = igb->default_mtu +
1104 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM;
1105 igb->rx_buf_size = ((rx_size >> 10) + ((rx_size &
1111 tx_size = igb->max_frame_size;
1112 igb->tx_buf_size = ((tx_size >> 10) + ((tx_size &
1117 err = igb_set_priv_prop(igb, pr_name, pr_valsize, pr_val);
1124 mutex_exit(&igb->gen_lock);
1126 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
1127 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
1138 igb_t *igb = (igb_t *)arg;
1139 struct e1000_hw *hw = &igb->hw;
1147 bcopy(&igb->link_duplex, pr_val, sizeof (link_duplex_t));
1151 tmp = igb->link_speed * 1000000ull;
1156 *(uint8_t *)pr_val = igb->param_adv_autoneg_cap;
1177 *(uint8_t *)pr_val = igb->param_adv_1000fdx_cap;
1180 *(uint8_t *)pr_val = igb->param_en_1000fdx_cap;
1183 *(uint8_t *)pr_val = igb->param_adv_1000hdx_cap;
1186 *(uint8_t *)pr_val = igb->param_en_1000hdx_cap;
1189 *(uint8_t *)pr_val = igb->param_adv_100t4_cap;
1192 *(uint8_t *)pr_val = igb->param_en_100t4_cap;
1195 *(uint8_t *)pr_val = igb->param_adv_100fdx_cap;
1198 *(uint8_t *)pr_val = igb->param_en_100fdx_cap;
1201 *(uint8_t *)pr_val = igb->param_adv_100hdx_cap;
1204 *(uint8_t *)pr_val = igb->param_en_100hdx_cap;
1207 *(uint8_t *)pr_val = igb->param_adv_10fdx_cap;
1210 *(uint8_t *)pr_val = igb->param_en_10fdx_cap;
1213 *(uint8_t *)pr_val = igb->param_adv_10hdx_cap;
1216 *(uint8_t *)pr_val = igb->param_en_10hdx_cap;
1219 err = igb_get_priv_prop(igb, pr_name, pr_valsize, pr_val);
1232 igb_t *igb = (igb_t *)arg;
1233 struct e1000_hw *hw = &igb->hw;
1324 igb_priv_prop_info(igb, pr_name, prh);
1354 igb_set_priv_prop(igb_t *igb, const char *pr_name,
1359 struct e1000_hw *hw = &igb->hw;
1409 igb->tx_copy_thresh = (uint32_t)result;
1423 igb->tx_recycle_thresh = (uint32_t)result;
1437 igb->tx_overload_thresh = (uint32_t)result;
1449 result > igb->tx_ring_size)
1452 igb->tx_resched_thresh = (uint32_t)result;
1466 igb->rx_copy_thresh = (uint32_t)result;
1480 igb->rx_limit_per_intr = (uint32_t)result;
1491 if (result < igb->capab->min_intr_throttle ||
1492 result > igb->capab->max_intr_throttle)
1495 igb->intr_throttling[0] = (uint32_t)result;
1498 igb->intr_throttling[i] =
1499 igb->intr_throttling[0];
1502 for (i = 0; i < igb->intr_cnt; i++)
1504 igb->intr_throttling[i]);
1512 igb_get_priv_prop(igb_t *igb, const char *pr_name, uint_t pr_valsize,
1518 value = igb->param_adv_pause_cap;
1520 value = igb->param_adv_asym_pause_cap;
1526 switch (igb->hw.mac.type) {
1529 value = !(igb->hw.dev_spec._82575.eee_disable);
1535 value = igb->tx_copy_thresh;
1537 value = igb->tx_recycle_thresh;
1539 value = igb->tx_overload_thresh;
1541 value = igb->tx_resched_thresh;
1543 value = igb->rx_copy_thresh;
1545 value = igb->rx_limit_per_intr;
1547 value = igb->intr_throttling[0];
1557 igb_priv_prop_info(igb_t *igb, const char *pr_name, mac_prop_info_handle_t prh)
1579 value = igb->capab->def_intr_throttle;