Lines Matching refs:state
94 static int tavor_rsrc_mbox_init(tavor_state_t *state,
96 static void tavor_rsrc_mbox_fini(tavor_state_t *state,
99 static int tavor_rsrc_hw_entries_init(tavor_state_t *state,
101 static void tavor_rsrc_hw_entries_fini(tavor_state_t *state,
104 static int tavor_rsrc_sw_handles_init(tavor_state_t *state,
106 static void tavor_rsrc_sw_handles_fini(tavor_state_t *state,
109 static int tavor_rsrc_pd_handles_init(tavor_state_t *state,
111 static void tavor_rsrc_pd_handles_fini(tavor_state_t *state,
147 static void tavor_rsrc_pdhdl_destructor(void *pd, void *state);
149 static void tavor_rsrc_cqhdl_destructor(void *cq, void *state);
151 static void tavor_rsrc_qphdl_destructor(void *cq, void *state);
153 static void tavor_rsrc_srqhdl_destructor(void *srq, void *state);
155 static void tavor_rsrc_refcnt_destructor(void *rc, void *state);
157 static void tavor_rsrc_ahhdl_destructor(void *ah, void *state);
159 static void tavor_rsrc_mrhdl_destructor(void *mr, void *state);
166 static int tavor_rsrc_mcg_entry_get_size(tavor_state_t *state,
178 tavor_rsrc_alloc(tavor_state_t *state, tavor_rsrc_type_t rsrc, uint_t num,
187 ASSERT(state != NULL);
190 rsrc_pool = &state->ts_rsrc_hdl[rsrc];
197 tmp_rsrc_hdl = (tavor_rsrc_t *)kmem_cache_alloc(state->ts_rsrc_cache,
246 state->ts_reg_ddrhdl, sleepflag, tmp_rsrc_hdl);
272 state->ts_reg_ddrhdl, sleepflag, tmp_rsrc_hdl);
282 state->ts_reg_uarhdl, sleepflag, tmp_rsrc_hdl);
302 TAVOR_WARNING(state, "unexpected resource type in alloc");
314 kmem_cache_free(state->ts_rsrc_cache, tmp_rsrc_hdl);
333 tavor_rsrc_free(tavor_state_t *state, tavor_rsrc_t **hdl)
339 ASSERT(state != NULL);
342 rsrc_pool = &state->ts_rsrc_hdl[(*hdl)->rsrc_type];
384 TAVOR_WARNING(state, "unexpected resource type in free");
394 kmem_cache_free(state->ts_rsrc_cache, *hdl);
419 tavor_rsrc_init_phase1(tavor_state_t *state)
431 ASSERT(state != NULL);
444 state->ts_rsrc_cache = kmem_cache_create(rsrc_name,
451 state->ts_rsrc_hdl = kmem_zalloc(TAVOR_NUM_RESOURCES *
454 cfgprof = state->ts_cfg_profile;
465 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_OUT_MBOX];
472 rsrc_pool->rsrc_state = state;
478 status = tavor_rsrc_mbox_init(state, &mbox_info);
480 tavor_rsrc_fini(state, cleanup);
494 status = tavor_outmbox_list_init(state);
496 tavor_rsrc_fini(state, cleanup);
512 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_INTR_OUT_MBOX];
519 rsrc_pool->rsrc_state = state;
525 status = tavor_rsrc_mbox_init(state, &mbox_info);
527 tavor_rsrc_fini(state, cleanup);
541 status = tavor_intr_outmbox_list_init(state);
543 tavor_rsrc_fini(state, cleanup);
568 tavor_rsrc_init_phase2(tavor_state_t *state)
585 ASSERT(state != NULL);
596 ddr_size = state->ts_ddr.ddr_endaddr - state->ts_ddr.ddr_baseaddr + 1;
597 fw_size = state->ts_fw.fw_endaddr - state->ts_fw.fw_baseaddr + 1;
609 state->ts_ddrvmem = vmem_create(rsrc_name,
610 (void *)(uintptr_t)state->ts_ddr.ddr_baseaddr, (ddr_size - fw_size),
612 if (state->ts_ddrvmem == NULL) {
613 tavor_rsrc_fini(state, cleanup);
625 cfgprof = state->ts_cfg_profile;
635 max = ((uint64_t)1 << state->ts_devlim.log_max_mpt);
636 num_prealloc = ((uint64_t)1 << state->ts_devlim.log_rsvd_mpt);
637 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_MPT];
644 rsrc_pool->rsrc_state = state;
652 status = tavor_rsrc_hw_entries_init(state, &entry_info);
654 tavor_rsrc_fini(state, cleanup);
670 max = ((uint64_t)1 << state->ts_devlim.log_max_mttseg);
671 num_prealloc = ((uint64_t)1 << state->ts_devlim.log_rsvd_mttseg);
672 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_MTT];
679 rsrc_pool->rsrc_state = state;
687 status = tavor_rsrc_hw_entries_init(state, &entry_info);
689 tavor_rsrc_fini(state, cleanup);
704 max = ((uint64_t)1 << state->ts_devlim.log_max_qp);
705 num_prealloc = ((uint64_t)1 << state->ts_devlim.log_rsvd_qp);
706 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_QPC];
713 rsrc_pool->rsrc_state = state;
721 status = tavor_rsrc_hw_entries_init(state, &entry_info);
723 tavor_rsrc_fini(state, cleanup);
737 max = ((uint64_t)1 << state->ts_devlim.log_max_ra_glob);
739 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_RDB];
746 rsrc_pool->rsrc_state = state;
754 status = tavor_rsrc_hw_entries_init(state, &entry_info);
756 tavor_rsrc_fini(state, cleanup);
771 max = ((uint64_t)1 << state->ts_devlim.log_max_cq);
772 num_prealloc = ((uint64_t)1 << state->ts_devlim.log_rsvd_cq);
773 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_CQC];
780 rsrc_pool->rsrc_state = state;
788 status = tavor_rsrc_hw_entries_init(state, &entry_info);
790 tavor_rsrc_fini(state, cleanup);
809 max = ((uint64_t)1 << state->ts_devlim.log_max_qp);
811 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_EQPC];
818 rsrc_pool->rsrc_state = state;
826 status = tavor_rsrc_hw_entries_init(state, &entry_info);
828 tavor_rsrc_fini(state, cleanup);
842 max = ((uint64_t)1 << state->ts_devlim.log_max_av);
844 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_UDAV];
851 rsrc_pool->rsrc_state = state;
859 status = tavor_rsrc_hw_entries_init(state, &entry_info);
861 tavor_rsrc_fini(state, cleanup);
879 uarscr_size = state->ts_devlim.uarscr_entry_sz;
881 max = ((uint64_t)1 << (state->ts_devlim.log_max_uar_sz + 20 -
884 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_UAR_SCR];
891 rsrc_pool->rsrc_state = state;
899 status = tavor_rsrc_hw_entries_init(state, &entry_info);
901 tavor_rsrc_fini(state, cleanup);
919 max = ((uint64_t)1 << state->ts_devlim.log_max_srq);
920 num_prealloc = ((uint64_t)1 << state->ts_devlim.log_rsvd_srq);
922 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_SRQC];
929 rsrc_pool->rsrc_state = state;
943 if (state->ts_cfg_profile->cp_srq_enable != 0) {
944 status = tavor_rsrc_hw_entries_init(state, &entry_info);
946 tavor_rsrc_fini(state, cleanup);
963 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_IN_MBOX];
970 rsrc_pool->rsrc_state = state;
976 status = tavor_rsrc_mbox_init(state, &mbox_info);
978 tavor_rsrc_fini(state, cleanup);
992 status = tavor_inmbox_list_init(state);
994 tavor_rsrc_fini(state, cleanup);
1010 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_INTR_IN_MBOX];
1017 rsrc_pool->rsrc_state = state;
1023 status = tavor_rsrc_mbox_init(state, &mbox_info);
1025 tavor_rsrc_fini(state, cleanup);
1039 status = tavor_intr_inmbox_list_init(state);
1041 tavor_rsrc_fini(state, cleanup);
1053 status = tavor_outstanding_cmdlist_init(state);
1055 tavor_rsrc_fini(state, cleanup);
1065 status = tavor_rsrc_mcg_entry_get_size(state, &mcg_size_shift);
1067 tavor_rsrc_fini(state, cleanup);
1072 mcg_size = TAVOR_MCGMEM_SZ(state);
1084 max = ((uint64_t)1 << state->ts_devlim.log_max_mcg);
1086 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_MCG];
1093 rsrc_pool->rsrc_state = state;
1101 status = tavor_rsrc_hw_entries_init(state, &entry_info);
1103 tavor_rsrc_fini(state, cleanup);
1117 max = ((uint64_t)1 << state->ts_devlim.log_max_eq);
1119 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_EQC];
1126 rsrc_pool->rsrc_state = state;
1134 status = tavor_rsrc_hw_entries_init(state, &entry_info);
1136 tavor_rsrc_fini(state, cleanup);
1157 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_PDHDL];
1161 rsrc_pool->rsrc_state = state;
1164 hdl_info.swi_max = ((uint64_t)1 << state->ts_devlim.log_max_pd);
1170 status = tavor_rsrc_pd_handles_init(state, &hdl_info);
1172 tavor_rsrc_fini(state, cleanup);
1185 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_MRHDL];
1189 rsrc_pool->rsrc_state = state;
1192 hdl_info.swi_max = ((uint64_t)1 << state->ts_devlim.log_max_mpt);
1198 status = tavor_rsrc_sw_handles_init(state, &hdl_info);
1200 tavor_rsrc_fini(state, cleanup);
1213 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_EQHDL];
1217 rsrc_pool->rsrc_state = state;
1220 hdl_info.swi_max = ((uint64_t)1 << state->ts_devlim.log_max_eq);
1226 status = tavor_rsrc_sw_handles_init(state, &hdl_info);
1228 tavor_rsrc_fini(state, cleanup);
1242 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_CQHDL];
1246 rsrc_pool->rsrc_state = state;
1249 hdl_info.swi_max = ((uint64_t)1 << state->ts_devlim.log_max_cq);
1257 status = tavor_rsrc_sw_handles_init(state, &hdl_info);
1259 tavor_rsrc_fini(state, cleanup);
1273 state->ts_cqhdl = hdl_info.swi_table_ptr;
1286 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_SRQHDL];
1290 rsrc_pool->rsrc_state = state;
1293 hdl_info.swi_max = ((uint64_t)1 << state->ts_devlim.log_max_srq);
1307 if (state->ts_cfg_profile->cp_srq_enable != 0) {
1308 status = tavor_rsrc_sw_handles_init(state, &hdl_info);
1310 tavor_rsrc_fini(state, cleanup);
1324 state->ts_srqhdl = hdl_info.swi_table_ptr;
1334 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_AHHDL];
1338 rsrc_pool->rsrc_state = state;
1341 hdl_info.swi_max = ((uint64_t)1 << state->ts_devlim.log_max_av);
1347 status = tavor_rsrc_sw_handles_init(state, &hdl_info);
1349 tavor_rsrc_fini(state, cleanup);
1363 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_QPHDL];
1367 rsrc_pool->rsrc_state = state;
1370 hdl_info.swi_max = ((uint64_t)1 << state->ts_devlim.log_max_qp);
1378 status = tavor_rsrc_sw_handles_init(state, &hdl_info);
1380 tavor_rsrc_fini(state, cleanup);
1394 state->ts_qphdl = hdl_info.swi_table_ptr;
1404 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_REFCNT];
1408 rsrc_pool->rsrc_state = state;
1411 hdl_info.swi_max = ((uint64_t)1 << state->ts_devlim.log_max_mpt);
1417 status = tavor_rsrc_sw_handles_init(state, &hdl_info);
1419 tavor_rsrc_fini(state, cleanup);
1433 hdl_info.swi_max = ((uint64_t)1 << state->ts_devlim.log_max_mcg);
1436 status = tavor_rsrc_sw_handles_init(state, &hdl_info);
1438 tavor_rsrc_fini(state, cleanup);
1443 state->ts_mcghdl = hdl_info.swi_table_ptr;
1463 max = ((uint64_t)1 << (state->ts_devlim.log_max_uar_sz + 20 -
1466 rsrc_pool = &state->ts_rsrc_hdl[TAVOR_UARPG];
1473 rsrc_pool->rsrc_state = state;
1474 rsrc_pool->rsrc_start = (void *)state->ts_reg_uar_baseaddr;
1481 status = tavor_rsrc_hw_entries_init(state, &entry_info);
1483 tavor_rsrc_fini(state, cleanup);
1508 tavor_rsrc_fini(tavor_state_t *state, tavor_rsrc_cleanup_level_t clean)
1517 ASSERT(state != NULL);
1519 cfgprof = state->ts_cfg_profile;
1529 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_UARPG];
1530 tavor_rsrc_hw_entries_fini(state, &entry_info);
1536 hdl_info.swi_table_ptr = state->ts_mcghdl;
1540 tavor_rsrc_sw_handles_fini(state, &hdl_info);
1545 hdl_info.swi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_REFCNT];
1547 tavor_rsrc_sw_handles_fini(state, &hdl_info);
1552 hdl_info.swi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_QPHDL];
1553 hdl_info.swi_table_ptr = state->ts_qphdl;
1557 tavor_rsrc_sw_handles_fini(state, &hdl_info);
1562 hdl_info.swi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_AHHDL];
1564 tavor_rsrc_sw_handles_fini(state, &hdl_info);
1574 if (state->ts_cfg_profile->cp_srq_enable != 0) {
1576 &state->ts_rsrc_hdl[TAVOR_SRQHDL];
1577 hdl_info.swi_table_ptr = state->ts_srqhdl;
1581 tavor_rsrc_sw_handles_fini(state, &hdl_info);
1587 hdl_info.swi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_CQHDL];
1588 hdl_info.swi_table_ptr = state->ts_cqhdl;
1592 tavor_rsrc_sw_handles_fini(state, &hdl_info);
1597 hdl_info.swi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_EQHDL];
1599 tavor_rsrc_sw_handles_fini(state, &hdl_info);
1604 hdl_info.swi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_MRHDL];
1606 tavor_rsrc_sw_handles_fini(state, &hdl_info);
1611 hdl_info.swi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_PDHDL];
1613 tavor_rsrc_pd_handles_fini(state, &hdl_info);
1618 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_EQC];
1619 tavor_rsrc_hw_entries_fini(state, &entry_info);
1624 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_MCG];
1625 tavor_rsrc_hw_entries_fini(state, &entry_info);
1630 tavor_outstanding_cmdlist_fini(state);
1635 tavor_intr_inmbox_list_fini(state);
1640 mbox_info.mbi_rsrcpool = &state->ts_rsrc_hdl[
1642 tavor_rsrc_mbox_fini(state, &mbox_info);
1647 tavor_inmbox_list_fini(state);
1652 mbox_info.mbi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_IN_MBOX];
1653 tavor_rsrc_mbox_fini(state, &mbox_info);
1663 if (state->ts_cfg_profile->cp_srq_enable != 0) {
1665 &state->ts_rsrc_hdl[TAVOR_SRQC];
1666 tavor_rsrc_hw_entries_fini(state, &entry_info);
1672 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_UAR_SCR];
1673 tavor_rsrc_hw_entries_fini(state, &entry_info);
1678 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_UDAV];
1679 tavor_rsrc_hw_entries_fini(state, &entry_info);
1684 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_EQPC];
1685 tavor_rsrc_hw_entries_fini(state, &entry_info);
1690 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_CQC];
1691 tavor_rsrc_hw_entries_fini(state, &entry_info);
1696 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_RDB];
1697 tavor_rsrc_hw_entries_fini(state, &entry_info);
1702 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_QPC];
1703 tavor_rsrc_hw_entries_fini(state, &entry_info);
1708 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_MTT];
1709 tavor_rsrc_hw_entries_fini(state, &entry_info);
1714 entry_info.hwi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_MPT];
1715 tavor_rsrc_hw_entries_fini(state, &entry_info);
1720 vmem_destroy(state->ts_ddrvmem);
1729 tavor_intr_outmbox_list_fini(state);
1734 mbox_info.mbi_rsrcpool = &state->ts_rsrc_hdl[
1736 tavor_rsrc_mbox_fini(state, &mbox_info);
1741 tavor_outmbox_list_fini(state);
1746 mbox_info.mbi_rsrcpool = &state->ts_rsrc_hdl[TAVOR_OUT_MBOX];
1747 tavor_rsrc_mbox_fini(state, &mbox_info);
1752 kmem_free(state->ts_rsrc_hdl, TAVOR_NUM_RESOURCES *
1754 kmem_cache_destroy(state->ts_rsrc_cache);
1758 TAVOR_WARNING(state, "unexpected resource cleanup level");
1773 tavor_rsrc_mbox_init(tavor_state_t *state, tavor_rsrc_mbox_info_t *info)
1783 ASSERT(state != NULL);
1789 dma_xfer_mode = state->ts_cfg_profile->cp_streaming_consistent;
1793 priv->pmb_dip = state->ts_dip;
1794 priv->pmb_acchdl = state->ts_reg_ddrhdl;
1795 priv->pmb_devaccattr = state->ts_reg_accattr;
1810 rsrc_pool->rsrc_ddr_offset = vmem_xalloc(state->ts_ddrvmem,
1824 state->ts_ddr.ddr_baseaddr);
1826 (void *)(uintptr_t)((uintptr_t)state->ts_reg_ddr_baseaddr +
1835 vmem_xfree(state->ts_ddrvmem,
1861 tavor_rsrc_mbox_fini(tavor_state_t *state, tavor_rsrc_mbox_info_t *info)
1867 ASSERT(state != NULL);
1880 vmem_xfree(state->ts_ddrvmem, rsrc_pool->rsrc_ddr_offset,
1896 tavor_rsrc_hw_entries_init(tavor_state_t *state,
1908 ASSERT(state != NULL);
1934 rsrc_pool->rsrc_ddr_offset = vmem_xalloc(state->ts_ddrvmem,
1947 state->ts_ddr.ddr_baseaddr);
1949 (void *)(uintptr_t)((uintptr_t)state->ts_reg_ddr_baseaddr +
1971 vmem_xfree(state->ts_ddrvmem,
1987 status = tavor_rsrc_alloc(state, rsrc_pool->rsrc_type,
1996 vmem_xfree(state->ts_ddrvmem,
2018 tavor_rsrc_hw_entries_fini(tavor_state_t *state,
2026 ASSERT(state != NULL);
2035 tavor_rsrc_free(state, &rsvd_rsrc);
2051 vmem_xfree(state->ts_ddrvmem, rsrc_pool->rsrc_ddr_offset,
2065 tavor_rsrc_sw_handles_init(tavor_state_t *state, tavor_rsrc_sw_hdl_info_t *info)
2072 ASSERT(state != NULL);
2119 tavor_rsrc_sw_handles_fini(tavor_state_t *state, tavor_rsrc_sw_hdl_info_t *info)
2126 ASSERT(state != NULL);
2155 tavor_rsrc_pd_handles_init(tavor_state_t *state, tavor_rsrc_sw_hdl_info_t *info)
2164 ASSERT(state != NULL);
2171 status = tavor_rsrc_sw_handles_init(state, info);
2187 tavor_rsrc_sw_handles_fini(state, info);
2205 tavor_rsrc_pd_handles_fini(tavor_state_t *state, tavor_rsrc_sw_hdl_info_t *info)
2211 ASSERT(state != NULL);
2220 tavor_rsrc_sw_handles_fini(state, info);
2571 tavor_state_t *state;
2576 state = (tavor_state_t *)priv;
2579 DDI_INTR_PRI(state->ts_intrmsi_pri));
2615 tavor_state_t *state;
2620 state = (tavor_state_t *)priv;
2623 DDI_INTR_PRI(state->ts_intrmsi_pri));
2625 DDI_INTR_PRI(state->ts_intrmsi_pri));
2662 tavor_state_t *state;
2667 state = (tavor_state_t *)priv;
2670 DDI_INTR_PRI(state->ts_intrmsi_pri));
2706 tavor_state_t *state;
2711 state = (tavor_state_t *)priv;
2714 DDI_INTR_PRI(state->ts_intrmsi_pri));
2750 tavor_state_t *state;
2755 state = (tavor_state_t *)priv;
2758 DDI_INTR_PRI(state->ts_intrmsi_pri));
2794 tavor_state_t *state;
2799 state = (tavor_state_t *)priv;
2802 DDI_INTR_PRI(state->ts_intrmsi_pri));
2838 tavor_state_t *state;
2843 state = (tavor_state_t *)priv;
2846 DDI_INTR_PRI(state->ts_intrmsi_pri));
2877 tavor_rsrc_mcg_entry_get_size(tavor_state_t *state, uint_t *mcg_size_shift)
2887 num_qp_per_mcg = state->ts_cfg_profile->cp_num_qp_per_mcg + 8;
2892 state->ts_cfg_profile->cp_num_qp_per_mcg = (1 << log2) - 8;
2895 num_qp_per_mcg = state->ts_cfg_profile->cp_num_qp_per_mcg;
2896 max_qp_per_mcg = (1 << state->ts_devlim.log_max_qp_mcg);