Lines Matching refs:state
45 /* Tavor HCA state pointer (extern) */
52 static int tavor_ioctl_flash_read(tavor_state_t *state, dev_t dev,
54 static int tavor_ioctl_flash_write(tavor_state_t *state, dev_t dev,
56 static int tavor_ioctl_flash_erase(tavor_state_t *state, dev_t dev,
58 static int tavor_ioctl_flash_init(tavor_state_t *state, dev_t dev,
60 static int tavor_ioctl_flash_fini(tavor_state_t *state, dev_t dev);
61 static void tavor_ioctl_flash_cleanup(tavor_state_t *state);
62 static void tavor_ioctl_flash_cleanup_nolock(tavor_state_t *state);
64 static int tavor_ioctl_reg_write(tavor_state_t *state, intptr_t arg,
66 static int tavor_ioctl_reg_read(tavor_state_t *state, intptr_t arg,
69 static int tavor_ioctl_info(tavor_state_t *state, dev_t dev,
71 static int tavor_ioctl_ports(tavor_state_t *state, intptr_t arg,
73 static int tavor_ioctl_loopback(tavor_state_t *state, intptr_t arg,
75 static int tavor_ioctl_ddr_read(tavor_state_t *state, intptr_t arg,
79 static void tavor_flash_read_sector(tavor_state_t *state, uint32_t sector_num);
80 static void tavor_flash_read_quadlet(tavor_state_t *state, uint32_t *data,
82 static int tavor_flash_write_sector(tavor_state_t *state, uint32_t sector_num);
83 static int tavor_flash_write_byte(tavor_state_t *state, uint32_t addr,
85 static int tavor_flash_erase_sector(tavor_state_t *state, uint32_t sector_num);
86 static int tavor_flash_erase_chip(tavor_state_t *state);
87 static void tavor_flash_bank(tavor_state_t *state, uint32_t addr);
88 static uint32_t tavor_flash_read(tavor_state_t *state, uint32_t addr);
89 static void tavor_flash_write(tavor_state_t *state, uint32_t addr,
91 static void tavor_flash_init(tavor_state_t *state);
92 static void tavor_flash_cfi_init(tavor_state_t *state, uint32_t *cfi_info,
94 static void tavor_flash_fini(tavor_state_t *state);
95 static void tavor_flash_reset(tavor_state_t *state);
106 static int tavor_loopback_init(tavor_state_t *state,
137 tavor_state_t *state;
156 state = ddi_get_soft_state(tavor_statep, instance);
157 if (state == NULL) {
167 status = tavor_ioctl_flash_read(state, dev, arg, mode);
171 status = tavor_ioctl_flash_write(state, dev, arg, mode);
175 status = tavor_ioctl_flash_erase(state, dev, arg, mode);
179 status = tavor_ioctl_flash_init(state, dev, arg, mode);
183 status = tavor_ioctl_flash_fini(state, dev);
187 status = tavor_ioctl_info(state, dev, arg, mode);
191 status = tavor_ioctl_ports(state, arg, mode);
195 status = tavor_ioctl_ddr_read(state, arg, mode);
199 status = tavor_ioctl_loopback(state, arg, mode);
204 status = tavor_ioctl_reg_write(state, arg, mode);
208 status = tavor_ioctl_reg_read(state, arg, mode);
227 tavor_ioctl_flash_read(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
238 mutex_enter(&state->ts_fw_flashlock);
239 if ((state->ts_fw_flashdev != dev) ||
240 (state->ts_fw_flashstarted == 0)) {
241 mutex_exit(&state->ts_fw_flashlock);
254 mutex_exit(&state->ts_fw_flashlock);
268 mutex_exit(&state->ts_fw_flashlock);
282 (state->ts_fw_device_sz >> state->ts_fw_log_sector_sz)) {
283 mutex_exit(&state->ts_fw_flashlock);
291 tavor_flash_reset(state);
292 tavor_flash_read_sector(state, ioctl_info.tf_sector_num);
295 if (ddi_copyout(&state->ts_fw_sector[0],
296 &ioctl_info.tf_sector[0], 1 << state->ts_fw_log_sector_sz,
298 mutex_exit(&state->ts_fw_flashlock);
308 if (ioctl_info.tf_addr >= state->ts_fw_device_sz) {
309 mutex_exit(&state->ts_fw_flashlock);
317 tavor_flash_reset(state);
318 tavor_flash_read_quadlet(state, &ioctl_info.tf_quadlet,
342 mutex_exit(&state->ts_fw_flashlock);
352 mutex_exit(&state->ts_fw_flashlock);
359 mutex_exit(&state->ts_fw_flashlock);
368 tavor_ioctl_flash_write(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
379 mutex_enter(&state->ts_fw_flashlock);
380 if ((state->ts_fw_flashdev != dev) ||
381 (state->ts_fw_flashstarted == 0)) {
382 mutex_exit(&state->ts_fw_flashlock);
395 mutex_exit(&state->ts_fw_flashlock);
410 mutex_exit(&state->ts_fw_flashlock);
424 (state->ts_fw_device_sz >> state->ts_fw_log_sector_sz)) {
425 mutex_exit(&state->ts_fw_flashlock);
434 &state->ts_fw_sector[0], 1 << state->ts_fw_log_sector_sz,
436 mutex_exit(&state->ts_fw_flashlock);
444 status = tavor_flash_write_sector(state,
450 if (ioctl_info.tf_addr >= state->ts_fw_device_sz) {
451 mutex_exit(&state->ts_fw_flashlock);
459 tavor_flash_bank(state, ioctl_info.tf_addr);
460 tavor_flash_reset(state);
461 status = tavor_flash_write_byte(state, ioctl_info.tf_addr,
463 tavor_flash_reset(state);
473 mutex_exit(&state->ts_fw_flashlock);
482 tavor_ioctl_flash_erase(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
493 mutex_enter(&state->ts_fw_flashlock);
494 if ((state->ts_fw_flashdev != dev) ||
495 (state->ts_fw_flashstarted == 0)) {
496 mutex_exit(&state->ts_fw_flashlock);
509 mutex_exit(&state->ts_fw_flashlock);
521 mutex_exit(&state->ts_fw_flashlock);
535 (state->ts_fw_device_sz >> state->ts_fw_log_sector_sz)) {
536 mutex_exit(&state->ts_fw_flashlock);
544 status = tavor_flash_erase_sector(state,
550 status = tavor_flash_erase_chip(state);
560 mutex_exit(&state->ts_fw_flashlock);
569 tavor_ioctl_flash_init(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
581 mutex_enter(&state->ts_fw_flashlock);
582 if (state->ts_fw_flashstarted == 1) {
583 mutex_exit(&state->ts_fw_flashlock);
593 mutex_exit(&state->ts_fw_flashlock);
601 tavor_flash_init(state);
604 tavor_flash_cfi_init(state, &init_info.tf_cfi_info[0], &intel_xcmd);
609 if (state->ts_fw_cmdset == TAVOR_FLASH_UNKNOWN_CMDSET) {
610 mutex_exit(&state->ts_fw_flashlock);
619 init_info.tf_hwrev = pci_config_get32(state->ts_pci_cfghdl,
623 init_info.tf_fwrev.tfi_maj = state->ts_fw.fw_rev_major;
624 init_info.tf_fwrev.tfi_min = state->ts_fw.fw_rev_minor;
625 init_info.tf_fwrev.tfi_sub = state->ts_fw.fw_rev_subminor;
628 state->ts_fw_sector = (uint32_t *)kmem_zalloc(1 <<
629 state->ts_fw_log_sector_sz, KM_SLEEP);
632 init_info.tf_pn_len = state->ts_hca_pn_len;
633 if (state->ts_hca_pn_len != 0) {
634 (void) memcpy(init_info.tf_hwpn, state->ts_hca_pn,
635 state->ts_hca_pn_len);
642 tavor_ioctl_flash_cleanup_nolock(state);
644 mutex_exit(&state->ts_fw_flashlock);
651 /* Set flash state to started */
652 state->ts_fw_flashstarted = 1;
653 state->ts_fw_flashdev = dev;
655 mutex_exit(&state->ts_fw_flashlock);
664 (void (*)(void *))tavor_ioctl_flash_cleanup, state);
666 (void) tavor_ioctl_flash_fini(state, dev);
682 tavor_ioctl_flash_fini(tavor_state_t *state, dev_t dev)
692 mutex_enter(&state->ts_fw_flashlock);
693 if ((state->ts_fw_flashdev != dev) ||
694 (state->ts_fw_flashstarted == 0)) {
695 mutex_exit(&state->ts_fw_flashlock);
701 tavor_ioctl_flash_cleanup_nolock(state);
703 mutex_exit(&state->ts_fw_flashlock);
727 tavor_ioctl_flash_cleanup(tavor_state_t *state)
731 mutex_enter(&state->ts_fw_flashlock);
732 tavor_ioctl_flash_cleanup_nolock(state);
733 mutex_exit(&state->ts_fw_flashlock);
743 tavor_ioctl_flash_cleanup_nolock(tavor_state_t *state)
747 ASSERT(MUTEX_HELD(&state->ts_fw_flashlock));
750 kmem_free(state->ts_fw_sector, 1 << state->ts_fw_log_sector_sz);
753 tavor_flash_fini(state);
755 /* Set flash state to fini */
756 state->ts_fw_flashstarted = 0;
757 state->ts_fw_flashdev = 0;
767 tavor_ioctl_info(tavor_state_t *state, dev_t dev, intptr_t arg, int mode)
777 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
808 mutex_enter(&state->ts_info_lock);
809 if (state->ts_fw_device_sz == 0) {
810 if (tavor_ioctl_flash_init(state, dev, (intptr_t)&init_info,
812 mutex_exit(&state->ts_info_lock);
818 (void) tavor_ioctl_flash_fini(state, dev);
820 mutex_exit(&state->ts_info_lock);
822 info.ti_hw_rev = state->ts_adapter.rev_id;
823 info.ti_flash_sz = state->ts_fw_device_sz;
824 info.ti_fw_rev.tfi_maj = state->ts_fw.fw_rev_major;
825 info.ti_fw_rev.tfi_min = state->ts_fw.fw_rev_minor;
826 info.ti_fw_rev.tfi_sub = state->ts_fw.fw_rev_subminor;
828 info.ti_mem_end_offset = state->ts_ddr.ddr_endaddr -
829 state->ts_ddr.ddr_baseaddr;
847 tavor_ioctl_ports(tavor_state_t *state, intptr_t arg, int mode)
862 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
905 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
908 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
918 info.tp_num_ports = (uint8_t)state->ts_cfg_profile->cp_num_ports;
928 if (tavor_port_query(state, i + 1, &pi) != 0) {
951 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
953 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
990 tavor_ioctl_loopback(tavor_state_t *state, intptr_t arg, int mode)
1007 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
1046 /* Initialize the internal loopback test state structure */
1062 if (!tavor_portnum_is_valid(state, lb.tlb_port_num)) {
1072 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
1075 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
1085 if (tavor_port_query(state, lb.tlb_port_num, &pi) != 0) {
1087 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
1089 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
1104 lstate.tls_state = state;
1108 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_gidtbl);
1110 tbl_size = (1 << state->ts_cfg_profile->cp_log_max_pkeytbl);
1143 if (tavor_loopback_init(state, &lstate) != 0) {
1329 tavor_ioctl_ddr_read(tavor_state_t *state, intptr_t arg, int mode)
1341 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
1369 ddr_size = (state->ts_ddr.ddr_endaddr - state->ts_ddr.ddr_baseaddr + 1);
1378 baseaddr = (uintptr_t)state->ts_reg_ddr_baseaddr;
1384 rdreg.tdr_data = ddi_get32(state->ts_reg_cmdhdl, addr);
1405 tavor_ioctl_reg_read(tavor_state_t *state, intptr_t arg, int mode)
1418 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
1438 baseaddr = (uintptr_t)state->ts_reg_cmd_baseaddr;
1442 baseaddr = (uintptr_t)state->ts_reg_uar_baseaddr;
1446 baseaddr = (uintptr_t)state->ts_reg_ddr_baseaddr;
1460 rdreg.trg_data = ddi_get32(state->ts_reg_cmdhdl, addr);
1481 tavor_ioctl_reg_write(tavor_state_t *state, intptr_t arg, int mode)
1494 if (state->ts_operational_mode == TAVOR_MAINTENANCE_MODE) {
1514 baseaddr = (uintptr_t)state->ts_reg_cmd_baseaddr;
1518 baseaddr = (uintptr_t)state->ts_reg_uar_baseaddr;
1522 baseaddr = (uintptr_t)state->ts_reg_ddr_baseaddr;
1536 ddi_put32(state->ts_reg_cmdhdl, addr, wrreg.trg_data);
1547 tavor_flash_reset(tavor_state_t *state)
1555 switch (state->ts_fw_cmdset) {
1557 tavor_flash_write(state, 0x555, TAVOR_HW_FLASH_RESET_AMD);
1561 tavor_flash_write(state, 0x555, TAVOR_HW_FLASH_RESET_INTEL);
1575 tavor_flash_read_sector(tavor_state_t *state, uint32_t sector_num)
1584 image = (uint32_t *)&state->ts_fw_sector[0];
1590 addr = sector_num << state->ts_fw_log_sector_sz;
1591 end_addr = addr + (1 << state->ts_fw_log_sector_sz);
1594 tavor_flash_bank(state, addr);
1598 image[i] = tavor_flash_read(state, addr);
1608 tavor_flash_read_quadlet(tavor_state_t *state, uint32_t *data,
1614 tavor_flash_bank(state, addr);
1617 *data = tavor_flash_read(state, addr);
1626 tavor_flash_write_sector(tavor_state_t *state, uint32_t sector_num)
1636 sector = (uchar_t *)&state->ts_fw_sector[0];
1642 addr = sector_num << state->ts_fw_log_sector_sz;
1643 end_addr = addr + (1 << state->ts_fw_log_sector_sz);
1646 tavor_flash_bank(state, addr);
1649 tavor_flash_reset(state);
1650 status = tavor_flash_erase_sector(state, sector_num);
1658 status = tavor_flash_write_byte(state, addr, sector[i]);
1664 tavor_flash_reset(state);
1673 tavor_flash_write_byte(tavor_state_t *state, uint32_t addr, uchar_t data)
1681 switch (state->ts_fw_cmdset) {
1684 tavor_flash_write(state, addr, 0xAA);
1685 tavor_flash_write(state, addr, 0x55);
1686 tavor_flash_write(state, addr, 0xA0);
1687 tavor_flash_write(state, addr, data);
1700 stat = tavor_flash_read(state, addr & ~3);
1717 tavor_flash_write(state, addr, TAVOR_HW_FLASH_ICS_WRITE);
1718 tavor_flash_write(state, addr, data);
1724 stat = tavor_flash_read(state, addr & ~3);
1750 state->ts_fw_cmdset);
1763 tavor_flash_erase_sector(tavor_state_t *state, uint32_t sector_num)
1773 addr = sector_num << state->ts_fw_log_sector_sz;
1775 switch (state->ts_fw_cmdset) {
1778 tavor_flash_write(state, addr, 0xAA);
1779 tavor_flash_write(state, addr, 0x55);
1780 tavor_flash_write(state, addr, 0x80);
1781 tavor_flash_write(state, addr, 0xAA);
1782 tavor_flash_write(state, addr, 0x55);
1783 tavor_flash_write(state, addr, 0x30);
1798 stat = tavor_flash_read(state, addr);
1814 tavor_flash_write(state, addr, TAVOR_HW_FLASH_ICS_ERASE);
1815 tavor_flash_write(state, addr, TAVOR_HW_FLASH_ICS_CONFIRM);
1821 stat = tavor_flash_read(state, addr & ~3);
1845 state->ts_fw_cmdset);
1850 tavor_flash_reset(state);
1860 tavor_flash_erase_chip(tavor_state_t *state)
1870 switch (state->ts_fw_cmdset) {
1873 tavor_flash_write(state, 0, 0xAA);
1874 tavor_flash_write(state, 0, 0x55);
1875 tavor_flash_write(state, 0, 0x80);
1876 tavor_flash_write(state, 0, 0xAA);
1877 tavor_flash_write(state, 0, 0x55);
1878 tavor_flash_write(state, 0, 0x10);
1893 stat = tavor_flash_read(state, 0);
1911 size = (0x1 << state->ts_fw_log_sector_sz);
1912 num_sect = state->ts_fw_device_sz / size;
1915 status = tavor_flash_erase_sector(state, i);
1928 "unknown cmd set: 0x%x\n", state->ts_fw_cmdset);
1941 tavor_flash_bank(tavor_state_t *state, uint32_t addr)
1949 hdl = state->ts_pci_cfghdl;
1954 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(state->ts_fw_flashbank))
1962 if (state->ts_fw_flashbank != bank || addr == 0) {
1968 /* Save the bank state */
1969 state->ts_fw_flashbank = bank;
1979 tavor_flash_read(tavor_state_t *state, uint32_t addr)
1988 hdl = state->ts_pci_cfghdl;
2022 tavor_flash_write(tavor_state_t *state, uint32_t addr, uchar_t data)
2031 hdl = state->ts_pci_cfghdl;
2062 tavor_flash_init(tavor_state_t *state)
2072 hdl = state->ts_pci_cfghdl;
2100 state->ts_fw_gpio[0] = tavor_flash_read_cfg(hdl,
2102 state->ts_fw_gpio[1] = tavor_flash_read_cfg(hdl,
2104 state->ts_fw_gpio[2] = tavor_flash_read_cfg(hdl,
2106 state->ts_fw_gpio[3] = tavor_flash_read_cfg(hdl,
2110 gpio = state->ts_fw_gpio[0] | 0x70;
2113 gpio = state->ts_fw_gpio[1] & ~0x70;
2116 gpio = state->ts_fw_gpio[2] & ~0x70;
2124 tavor_flash_bank(state, 0);
2134 tavor_flash_cfi_init(tavor_state_t *state, uint32_t *cfi_info, int *intel_xcmd)
2158 tavor_flash_write(state, 0x55, TAVOR_FLASH_CFI_INIT);
2162 data = tavor_flash_read(state, i);
2168 state->ts_fw_cmdset = TAVOR_FLASH_UNKNOWN_CMDSET;
2180 state->ts_fw_cmdset = cfi_ch_info[0x13];
2181 if (state->ts_fw_cmdset != TAVOR_FLASH_INTEL_CMDSET &&
2182 state->ts_fw_cmdset != TAVOR_FLASH_AMD_CMDSET) {
2185 state->ts_fw_cmdset = TAVOR_FLASH_UNKNOWN_CMDSET;
2198 state->ts_fw_log_sector_sz = bit_count;
2201 state->ts_fw_device_sz = 0x1 << cfi_ch_info[0x27];
2204 tavor_flash_reset(state);
2226 cfi_ch_info[0x13] = state->ts_fw_cmdset;
2236 tavor_flash_fini(tavor_state_t *state)
2243 hdl = state->ts_pci_cfghdl;
2247 state->ts_fw_gpio[0]);
2249 state->ts_fw_gpio[1]);
2251 state->ts_fw_gpio[2]);
2253 state->ts_fw_gpio[3]);
2397 tavor_loopback_init(tavor_state_t *state, tavor_loopback_state_t *lstate)
2401 lstate->tls_hca_hdl = (ibc_hca_hdl_t)state;