Lines Matching refs:dprintf

69 #define	dprintf(x)	if (i8237debug) (void)prom_printf x
71 #define dprintf(x)
192 dprintf(("d37A_dma_disable: chnl=%d mask_reg=0x%x\n",
210 dprintf(("d37A_dma_enable: chnl=%d mask_reg=0x%x val=0x%x\n",
293 dprintf(("dEISA_setchain: chnl=%d next_addr=%x count=%lx\n",
303 dprintf(("dEISA_setchain: chnl=%d end\n", chnl));
321 dprintf(("d37A_prog_chan err: chnl=%d in cascade mode\n",
327 dprintf(("d37A_prog_chan err: memory to memory mode not supported.\n"));
332 dprintf(("d37A_prog_chan: chnl=%d dmaereq=%p\n",
344 dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));
359 dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));
366 dprintf(("d37A_prog_chan err: chnl %d not programmed.\n", chnl));
413 dprintf(("d37A_dma_swsetup err: chnl %d not programmed\n",
418 dprintf(("d37A_dma_swsetup: chnl=%d dmaereq=%p.\n",
432 dprintf(("d37A_dma_swsetup err: chnl %d not programmed.\n", chnl));
446 dprintf(("d37A_dma_swsetup err: chnl %d not programmed.\n", chnl));
453 dprintf(("d37A_dma_swsetup err: chnl %d not set up.\n", chnl));
492 dprintf(("d37A_dma_swstart: chnl=%d\n", chnl));
511 dprintf(("d37A_dma_stop: chnl=%d\n", chnl));
541 dprintf(("d37A_get_chan_stat: chnl=%d address=%lx count=%x\n",
605 dprintf(("d37A_set_mode: chnl=%d mode_reg=0x%x mode=0x%x\n",
647 dprintf(("d37A_set_mode: chnl=%d em_reg=0x%x emode=0x%x\n",
667 dprintf(("d37A_write_addr: chnl=%d address=%lx\n", chnl, paddress));
751 dprintf(("d37A_read_addr: chnl=%d address=%lx.\n", chnl, paddress));
769 dprintf(("d37A_write_count: chnl=%d count=0x%lx\n", chnl, count));
850 dprintf(("d37A_read_count: chnl=%d count=0x%lx\n", chnl, count));