Lines Matching defs:reg
217 uint32_t reg;
219 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK |
222 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg);
230 uint32_t reg;
232 reg = I40E_ITR_INDEX_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT;
233 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg);
239 uint32_t reg;
242 reg = I40E_PFINT_DYN_CTLN_INTENA_MASK |
245 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg);
251 uint32_t reg;
254 reg = I40E_ITR_INDEX_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
255 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg);
273 uint32_t reg;
276 reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE));
277 reg |= I40E_QINT_RQCTL_CAUSE_ENA_MASK;
278 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
280 reg = I40E_READ_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE));
281 reg |= I40E_QINT_TQCTL_CAUSE_ENA_MASK;
282 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
301 uint32_t reg;
304 reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE));
305 reg &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
306 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
308 reg = I40E_READ_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE));
309 reg &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
310 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
328 uint32_t reg;
329 reg = I40E_QUEUE_TYPE_EOL;
330 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, reg);
335 uint32_t reg;
341 reg = I40E_READ_REG(hw, I40E_PFINT_DYN_CTLN(i - 1));
342 VERIFY0(reg & I40E_PFINT_DYN_CTLN_INTENA_MASK);
344 reg = I40E_QUEUE_TYPE_EOL;
345 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(i - 1), reg);
359 uint32_t reg;
369 reg = I40E_READ_REG(hw, I40E_PFINT_DYN_CTLN(i - 1));
370 VERIFY0(reg & I40E_PFINT_DYN_CTLN_INTENA_MASK);
372 reg = I40E_READ_REG(hw, I40E_PFINT_LNKLSTN(i - 1));
373 VERIFY3U(reg, ==, I40E_QUEUE_TYPE_EOL);
390 uint32_t reg;
398 reg = (0 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
400 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(0), reg);
402 reg = (1 << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
408 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(0), reg);
410 reg = (1 << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
416 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(0), reg);
430 uint32_t reg;
435 reg = (I40E_INTR_NOTX_QUEUE << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
437 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, reg);
439 reg = (I40E_INTR_NOTX_INTR << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
445 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
447 reg = (I40E_INTR_NOTX_INTR << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
453 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
464 uint32_t reg;
470 reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(queue));
471 ASSERT0(reg & I40E_QINT_RQCTL_CAUSE_ENA_MASK);
472 reg |= I40E_QINT_RQCTL_CAUSE_ENA_MASK;
473 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(queue), reg);
484 uint32_t reg;
490 reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(queue));
491 ASSERT3U(reg & I40E_QINT_RQCTL_CAUSE_ENA_MASK, ==,
493 reg &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
494 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(queue), reg);
506 uint32_t reg;
521 reg = I40E_ITR_INDEX_OTHER << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT;
522 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0, reg);
530 reg = I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
531 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, reg);
638 uint32_t reg;
640 reg = I40E_READ_REG(hw, I40E_PFINT_ICR0);
648 if (reg & I40E_PFINT_ICR0_ADMINQ_MASK)
655 reg = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
656 reg |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
657 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, reg);
700 uint32_t reg;
712 reg = I40E_READ_REG(hw, I40E_PFINT_ICR0);
720 if (reg == 0) {
726 if (reg & I40E_PFINT_ICR0_ADMINQ_MASK)
729 if (reg & I40E_INTR_NOTX_RX_MASK)
732 if (reg & I40E_INTR_NOTX_TX_MASK)