Lines Matching defs:queue
25 * - 'Other Interrupts', such as the administrative queue
28 * being posted to the administrative queue, unrecoverable ECC errors, and more.
29 * If we have something being posted to the administrative queue, then we go
59 * By default, the admin queue, which consists of the asynchronous other
71 * registers can also be used to enable and disable whether or not the queue is
75 * first queue must be programmed in I40E_QINT_LNKLSTN(%vector) register. Each
76 * queue defines the next one in either the I40E_QINT_RQCTL or I40E_QINT_TQCTL
79 * Because we only have a single queue enabled at the moment and we always have
81 * data queue in the interrupt handler. Longer term, we'll need to think harder
89 * Note that this means that both the individual queue and the interrupt as a
98 * queue pair and it is bound to the same interrupt with index zero. The
103 * In this world, because the interrupts for the admin queue and traffic are
107 * however, we only use the bit 0 and 1 for the rx and tx queue respectively.
111 * Unfortunately, these corresponding queue bits have no corresponding entry in
113 * end up enabling it on the queue registers rather than on the MSI-X registers.
132 * o 'Other interrupts' (link status change, admin queue, etc.)
208 * Re-enable the adminq. Note that the adminq doesn't have a traditional queue
261 * towards the queue's CAUSE_ENA bit and enable that.
289 * towards the queue's CAUSE_ENA bit and disable that.
315 * As part of disabling the tx and rx queue's we're technically supposed to
352 * Finalize interrupt handling. Mostly this disables the admin queue.
393 * Because we only have a single queue, just do something simple now.
421 * Set up a single queue to share the admin queue interrupt in the non-MSI-X
422 * world. Note we do not enable the queue as an interrupt cause at this time. We
457 * Enable the specified queue as a valid source of interrupts. Note, this should
462 i40e_intr_rx_queue_enable(i40e_t *i40e, uint_t queue)
468 ASSERT(queue < i40e->i40e_num_trqpairs);
470 reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(queue));
473 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(queue), reg);
477 * Disable the specified queue as a valid source of interrupts. Note, this
482 i40e_intr_rx_queue_disable(i40e_t *i40e, uint_t queue)
488 ASSERT(queue < i40e->i40e_num_trqpairs);
490 reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(queue));
494 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(queue), reg);
602 i40e_intr_rx_work(i40e_t *i40e, int queue)
607 ASSERT(queue < i40e->i40e_num_trqpairs);
608 itrq = &i40e->i40e_trqpairs[queue];
621 i40e_intr_tx_work(i40e_t *i40e, int queue)
625 itrq = &i40e->i40e_trqpairs[queue];