Cross Reference: /illumos-gate/usr/src/uts/common/io/i40e/i40e

Lines Matching defs:hw
187 	i40e_hw_t *hw = &i40e->i40e_hw_space;
198 		I40E_WRITE_REG(hw, I40E_PFINT_ITR0(itr), val);
203 		I40E_WRITE_REG(hw, I40E_PFINT_ITRN(itr, i - 1), val);
216 	i40e_hw_t *hw = &i40e->i40e_hw_space;
222 	I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg);
223 	i40e_flush(hw);
229 	i40e_hw_t *hw = &i40e->i40e_hw_space;
233 	I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg);
240 	i40e_hw_t *hw = &i40e->i40e_hw_space;
245 	I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg);
252 	i40e_hw_t *hw = &i40e->i40e_hw_space;
255 	I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg);
274 		i40e_hw_t *hw = &i40e->i40e_hw_space;
276 		reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE));
278 		I40E_WRITE_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
280 		reg = I40E_READ_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE));
282 		I40E_WRITE_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
302 		i40e_hw_t *hw = &i40e->i40e_hw_space;
304 		reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE));
306 		I40E_WRITE_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
308 		reg = I40E_READ_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE));
310 		I40E_WRITE_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
325 	i40e_hw_t *hw = &i40e->i40e_hw_space;
330 		I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, reg);
341 		reg = I40E_READ_REG(hw, I40E_PFINT_DYN_CTLN(i - 1));
345 		I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(i - 1), reg);
348 	i40e_flush(hw);
361 	i40e_hw_t *hw = &i40e->i40e_hw_space;
369 			reg = I40E_READ_REG(hw, I40E_PFINT_DYN_CTLN(i - 1));
372 			reg = I40E_READ_REG(hw, I40E_PFINT_LNKLSTN(i - 1));
389 	i40e_hw_t *hw = &i40e->i40e_hw_space;
400 	I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(0), reg);
408 	I40E_WRITE_REG(hw, I40E_QINT_RQCTL(0), reg);
416 	I40E_WRITE_REG(hw, I40E_QINT_TQCTL(0), reg);
429 	i40e_hw_t *hw = &i40e->i40e_hw_space;
437 	I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, reg);
445 	I40E_WRITE_REG(hw, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg);
453 	I40E_WRITE_REG(hw, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg);
465 	i40e_hw_t *hw = &i40e->i40e_hw_space;
470 	reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(queue));
473 	I40E_WRITE_REG(hw, I40E_QINT_RQCTL(queue), reg);
485 	i40e_hw_t *hw = &i40e->i40e_hw_space;
490 	reg = I40E_READ_REG(hw, I40E_QINT_RQCTL(queue));
494 	I40E_WRITE_REG(hw, I40E_QINT_RQCTL(queue), reg);
505 	i40e_hw_t *hw = &i40e->i40e_hw_space;
513 	I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, 0);
514 	(void) I40E_READ_REG(hw, I40E_PFINT_ICR0);
522 	I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0, reg);
531 	I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, reg);
537 	I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_TYPE_EOL);
563 	struct i40e_hw *hw = &i40e->i40e_hw_space;
580 		ret = i40e_clean_arq_element(hw, &evt, &remain);
637 	struct i40e_hw *hw = &i40e->i40e_hw_space;
640 	reg = I40E_READ_REG(hw, I40E_PFINT_ICR0);
655 	reg = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
657 	I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, reg);
699 	i40e_hw_t *hw = &i40e->i40e_hw_space;
712 	reg = I40E_READ_REG(hw, I40E_PFINT_ICR0);