Lines Matching defs:settings
1456 * Make sure all PXE mode settings are cleared, including things
1728 /* clear the old pause settings */
1735 /* Auto restart link so settings take effect */
1738 /* Copy over all the old settings */
1773 * Configure MAC settings for frame size, jumbo frame support and the
4494 * EMP will return when the shared RPB settings have been
4880 * @settings: Filter control settings
4882 * Check and validate the filter control settings passed.
4890 struct i40e_filter_control_settings *settings)
4898 /* Validate FCoE settings passed */
4899 switch (settings->fcoe_filt_num) {
4907 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4913 switch (settings->fcoe_cntx_num) {
4919 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4925 /* Validate PE settings passed */
4926 switch (settings->pe_filt_num) {
4939 pe_filt_size <<= (u32)settings->pe_filt_num;
4945 switch (settings->pe_cntx_num) {
4957 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4976 * @settings: Filter control settings
4979 * for a single PF. It is expected that these settings are programmed
4983 struct i40e_filter_control_settings *settings)
4989 if (!settings)
4992 /* Validate the input settings */
4993 ret = i40e_validate_filter_settings(hw, settings);
5002 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5006 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5011 val |= ((u32)settings->fcoe_filt_num <<
5016 val |= ((u32)settings->fcoe_cntx_num <<
5022 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5028 if (settings->enable_fdir)
5030 if (settings->enable_ethtype)
5032 if (settings->enable_macvlan)