Lines Matching defs:hxgep
58 hxge_get_config_properties(p_hxge_t hxgep)
62 HXGE_DEBUG_MSG((hxgep, VPD_CTL, " ==> hxge_get_config_properties"));
64 if (hxgep->hxge_hw_p == NULL) {
65 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
70 hxgep->classifier.tcam_size = TCAM_HXGE_TCAM_MAX_ENTRY;
72 status = hxge_get_mac_addr_properties(hxgep);
74 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
79 HXGE_DEBUG_MSG((hxgep, VPD_CTL,
82 hxge_use_cfg_hydra_properties(hxgep);
84 HXGE_DEBUG_MSG((hxgep, VPD_CTL, " <== hxge_get_config_properties"));
90 hxge_set_hw_vlan_class_config(p_hxge_t hxgep)
103 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_set_hw_vlan_config"));
104 p_class_cfgp = (p_hxge_class_pt_cfg_t)&hxgep->class_config;
106 param_arr = hxgep->param_arr;
117 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip, 0, prop,
125 HXGE_DEBUG_MSG((hxgep, CFG2_CTL,
139 hxgep->dip, prop, (int *)good_cfg, good_count);
142 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_set_hw_vlan_config"));
152 hxge_use_cfg_vlan_class_config(p_hxge_t hxgep)
164 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_use_cfg_vlan_config"));
165 param_arr = hxgep->param_arr;
168 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip, 0, prop,
172 hxgep->dip, prop, vlan_cfg_val, vlan_cnt);
178 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip, 0, prop,
183 status = ddi_prop_update_int(DDI_DEV_T_NONE, hxgep->dip,
189 hxge_set_hw_vlan_class_config(hxgep);
191 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_use_cfg_vlan_config"));
200 hxge_use_cfg_hydra_properties(p_hxge_t hxgep)
202 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_use_cfg_hydra_properties"));
204 (void) hxge_use_cfg_dma_config(hxgep);
205 (void) hxge_use_cfg_vlan_class_config(hxgep);
206 (void) hxge_use_cfg_class_config(hxgep);
212 (void) hxge_get_param_soft_properties(hxgep);
213 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_use_cfg_hydra_properties"));
224 hxge_use_cfg_dma_config(p_hxge_t hxgep)
235 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_use_cfg_dma_config"));
236 param_arr = hxgep->param_arr;
238 p_dma_cfgp = (p_hxge_dma_pt_cfg_t)&hxgep->pt_config;
240 dip = hxgep->dip;
244 p_cfgp->max_tdcs = hxgep->max_tdcs = tx_ndmas;
245 hxgep->tdc_mask = (tx_ndmas - 1);
246 HXGE_DEBUG_MSG((hxgep, CFG_CTL, "==> hxge_use_cfg_dma_config: "
247 "p_cfgp 0x%llx max_tdcs %d hxgep->max_tdcs %d",
248 p_cfgp, p_cfgp->max_tdcs, hxgep->max_tdcs));
252 p_cfgp->max_rdcs = hxgep->max_rdcs = rx_ndmas;
257 HXGE_DEBUG_MSG((hxgep, CFG_CTL, "==> hxge_use_default_dma_config: "
258 "p_cfgp 0x%llx max_rdcs %d hxgep->max_rdcs %d",
259 p_cfgp, p_cfgp->max_rdcs, hxgep->max_rdcs));
261 HXGE_DEBUG_MSG((hxgep, CFG_CTL, "==> hxge_use_cfg_dma_config: "
262 "p_cfgp 0x%016llx start_ldg %d hxgep->max_ldgs %d ",
274 hxgep->dip, prop, prop_val, prop_len);
285 hxgep->dip, prop, prop_val, prop_len);
296 hxgep->dip, prop, prop_val, prop_len);
301 hxge_set_hw_dma_config(hxgep);
302 HXGE_DEBUG_MSG((hxgep, CFG_CTL, "<== hxge_use_cfg_dma_config"));
306 hxge_use_cfg_class_config(p_hxge_t hxgep)
308 hxge_set_hw_class_config(hxgep);
312 hxge_set_hw_dma_config(p_hxge_t hxgep)
317 HXGE_DEBUG_MSG((hxgep, CFG_CTL, "==> hxge_set_hw_dma_config"));
319 p_dma_cfgp = (p_hxge_dma_pt_cfg_t)&hxgep->pt_config;
323 hxgep->ntdc = p_cfgp->max_tdcs;
326 hxgep->nrdc = p_cfgp->max_rdcs;
333 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_set_hw_dma_config"));
338 hxge_check_rxdma_port_member(p_hxge_t hxgep, uint8_t rdc)
344 HXGE_DEBUG_MSG((hxgep, CFG2_CTL, "==> hxge_check_rxdma_port_member"));
346 p_dma_cfgp = (p_hxge_dma_pt_cfg_t)&hxgep->pt_config;
352 HXGE_DEBUG_MSG((hxgep, CFG2_CTL, " <== hxge_check_rxdma_port_member"));
358 hxge_check_txdma_port_member(p_hxge_t hxgep, uint8_t tdc)
364 HXGE_DEBUG_MSG((hxgep, CFG2_CTL, "==> hxge_check_txdma_port_member"));
366 p_dma_cfgp = (p_hxge_dma_pt_cfg_t)&hxgep->pt_config;
372 HXGE_DEBUG_MSG((hxgep, CFG2_CTL, " <== hxge_check_txdma_port_member"));
384 hxge_set_hw_class_config(p_hxge_t hxgep)
395 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_set_hw_class_config"));
397 p_class_cfgp = (p_hxge_class_pt_cfg_t)&hxgep->class_config;
399 param_arr = hxgep->param_arr;
409 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip,
430 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip,
444 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip, 0, prop,
454 HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_set_hw_class_config"));
462 hxge_ldgv_init(p_hxge_t hxgep, int *navail_p, int *nrequired_p)
475 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_ldgv_init"));
478 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
482 p_dma_cfgp = (p_hxge_dma_pt_cfg_t)&hxgep->pt_config;
502 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "<== hxge_ldgv_init: "
506 ldgvp = hxgep->ldgvp;
509 hxgep->ldgvp = ldgvp;
521 HXGE_DEBUG_MSG((hxgep, INT_CTL,
534 ptr->hxgep = hxgep;
535 HXGE_DEBUG_MSG((hxgep, INT_CTL,
538 HXGE_DEBUG_MSG((hxgep, INT_CTL,
578 ldvp->hxgep = hxgep;
597 ldvp->hxgep = hxgep;
611 ldvp->hxgep = hxgep;
615 HXGE_DEBUG_MSG((hxgep, INT_CTL,
628 ldvp->hxgep = hxgep;
632 HXGE_DEBUG_MSG((hxgep, INT_CTL,
644 ldvp->hxgep = hxgep;
655 HXGE_REG_WR32(hxgep->hpi_handle, PEU_INTR_MASK, parity_err_mask.value);
660 (void) hxge_fzc_sys_err_mask_set(hxgep, B_FALSE);
666 HXGE_DEBUG_MSG((hxgep, INT_CTL,
669 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_ldgv_init"));
674 hxge_ldgv_uninit(p_hxge_t hxgep)
678 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_ldgv_uninit"));
679 ldgvp = hxgep->ldgvp;
681 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
694 hxgep->ldgvp = NULL;
696 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_ldgv_uninit"));
701 hxge_intr_ldgv_init(p_hxge_t hxgep)
705 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr_ldgv_init"));
710 status = hxge_fzc_intr_init(hxgep);
715 status = hxge_intr_mask_mgmt(hxgep);
717 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intr_ldgv_init"));
722 hxge_intr_mask_mgmt(p_hxge_t hxgep)
731 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr_mask_mgmt"));
733 if ((ldgvp = hxgep->ldgvp) == NULL) {
734 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
738 handle = HXGE_DEV_HPI_HANDLE(hxgep);
742 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
747 HXGE_DEBUG_MSG((hxgep, INT_CTL,
750 HXGE_DEBUG_MSG((hxgep, INT_CTL,
753 HXGE_DEBUG_MSG((hxgep, INT_CTL,
757 HXGE_DEBUG_MSG((hxgep, INT_CTL,
763 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
769 HXGE_DEBUG_MSG((hxgep, INT_CTL,
778 for (i = 0; i < hxgep->ldgvp->ldg_intrs; i++, ldgp++) {
782 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
788 HXGE_DEBUG_MSG((hxgep, INT_CTL,
794 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_mask_mgmt"));
799 hxge_intr_mask_mgmt_set(p_hxge_t hxgep, boolean_t on)
808 HXGE_DEBUG_MSG((hxgep, INT_CTL,
811 if ((ldgvp = hxgep->ldgvp) == NULL) {
812 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
816 handle = HXGE_DEV_HPI_HANDLE(hxgep);
820 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
827 HXGE_DEBUG_MSG((hxgep, INT_CTL,
831 HXGE_DEBUG_MSG((hxgep, INT_CTL,
836 HXGE_DEBUG_MSG((hxgep, INT_CTL,
841 HXGE_DEBUG_MSG((hxgep, INT_CTL,
848 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
854 HXGE_DEBUG_MSG((hxgep, INT_CTL,
863 for (i = 0; i < hxgep->ldgvp->ldg_intrs; i++, ldgp++) {
872 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
878 HXGE_DEBUG_MSG((hxgep, INT_CTL,
884 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intr_mask_mgmt_set"));
895 hxge_get_mac_addr_properties(p_hxge_t hxgep)
897 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_get_mac_addr_properties "));
899 (void) hxge_pfc_mac_addrs_get(hxgep);
900 hxgep->ouraddr = hxgep->factaddr;
902 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_get_mac_addr_properties "));