Lines Matching refs:mask
72 #define WRITE_TCAM_REG_MASK0(handle, mask) \
73 REG_PIO_WRITE64(handle, PFC_TCAM_MASK0, mask)
74 #define WRITE_TCAM_REG_MASK1(handle, mask) \
75 REG_PIO_WRITE64(handle, PFC_TCAM_MASK1, mask)
220 } key, mask;
227 #define mask_reg0 mask.regs.reg0
228 #define mask_reg1 mask.regs.reg1
232 #define mask0 mask.regs.reg0
233 #define mask1 mask.regs.reg1
244 #define ip4_class_mask mask.ipv4.class_code
245 #define ip4_class_mask_l mask.ipv4.class_code_l
246 #define ip4_blade_id_mask mask.ipv4.blade_id
247 #define ip4_noport_mask mask.ipv4.noport
248 #define ip4_proto_mask mask.ipv4.protocol
249 #define ip4_l4_hdr_mask mask.ipv4.l4_hdr
250 #define ip4_l4_hdr_mask_l mask.ipv4.l4_hdr_l
251 #define ip4_dest_mask mask.ipv4.ip_daddr
260 #define ip6_class_mask mask.ipv6.class_code
261 #define ip6_class_mask_l mask.ipv6.class_code_l
262 #define ip6_blade_id_mask mask.ipv6.blade_id
263 #define ip6_proto_mask mask.ipv6.protocol
264 #define ip6_l4_hdr_mask mask.ipv6.l4_hdr
265 #define ip6_l4_hdr_mask_l mask.ipv6.l4_hdr_l
272 #define ether_class_mask mask.enet.class_code
273 #define ether_class_mask_l mask.enet.class_code_l
274 #define ether_blade_id_mask mask.enet.blade_id
275 #define ether_ethframe_mask mask.enet.eframe