Lines Matching defs:hxgep
34 static hxge_status_t hxge_pfc_load_hash_table(p_hxge_t hxgep);
35 static uint32_t hxge_get_blade_id(p_hxge_t hxgep);
36 static hxge_status_t hxge_tcam_default_add_entry(p_hxge_t hxgep,
38 static hxge_status_t hxge_tcam_default_config(p_hxge_t hxgep);
41 hxge_classify_init(p_hxge_t hxgep)
45 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_classify_init"));
47 status = hxge_classify_init_sw(hxgep);
51 status = hxge_classify_init_hw(hxgep);
53 (void) hxge_classify_exit_sw(hxgep);
57 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_classify_init"));
63 hxge_classify_uninit(p_hxge_t hxgep)
65 return (hxge_classify_exit_sw(hxgep));
69 hxge_tcam_dump_entry(p_hxge_t hxgep, uint32_t location)
76 handle = hxgep->hpi_reg_handle;
79 bcopy((void *)&hxgep->classifier.tcam_entries[location].tce,
85 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
93 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "location %x\n"
101 hxge_get_tcam(p_hxge_t hxgep, p_mblk_t mp)
107 int stop_location = hxgep->classifier.tcam_size;
112 if ((location >= hxgep->classifier.tcam_size) || (location < -1)) {
113 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
119 stop_location = hxgep->classifier.tcam_size;
125 (void) hxge_tcam_dump_entry(hxgep, tcam_loc);
130 hxge_add_tcam_entry(p_hxge_t hxgep, flow_resource_t *flow_res)
136 hxge_put_tcam(p_hxge_t hxgep, p_mblk_t mp)
141 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
145 (void) hxge_add_tcam_entry(hxgep, fs);
149 hxge_get_blade_id(p_hxge_t hxgep)
153 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_get_blade_id"));
154 HXGE_REG_RD32(hxgep->hpi_reg_handle, PHY_DEBUG_TRAINING_VEC,
156 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_get_blade_id: id = %d",
163 hxge_tcam_default_add_entry(p_hxge_t hxgep, tcam_class_t class)
173 if ((hw_p = hxgep->hxge_hw_p) == NULL) {
174 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
190 key->blade_id = hxge_get_blade_id(hxgep);
201 handle = hxgep->hpi_reg_handle;
207 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
228 HXGE_DEBUG_MSG((hxgep, PFC_CTL,
235 (void *) &hxgep->classifier.tcam_entries[location].tce,
252 hxge_tcam_default_config(p_hxge_t hxgep)
258 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_tcam_default_config"));
266 status = hxge_tcam_default_add_entry(hxgep, class);
268 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
282 class_config = hxgep->class_config.class_cfg[class];
284 status = hxge_pfc_ip_class_config(hxgep, class, class_config);
286 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
294 status = hxge_pfc_config_tcam_enable(hxgep);
296 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_tcam_default_config"));
302 hxge_pfc_set_default_mac_addr(p_hxge_t hxgep)
306 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_pfc_set_default_mac_addr"));
308 MUTEX_ENTER(&hxgep->ouraddr_lock);
315 RW_ENTER_WRITER(&hxgep->filter_lock);
316 status = hxge_pfc_set_mac_address(hxgep,
317 HXGE_MAC_DEFAULT_ADDR_SLOT, &hxgep->ouraddr);
318 RW_EXIT(&hxgep->filter_lock);
320 MUTEX_EXIT(&hxgep->ouraddr_lock);
322 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_pfc_set_default_mac_addr"));
330 hxge_add_mcast_addr(p_hxge_t hxgep, struct ether_addr *addrp)
339 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_add_mcast_addr"));
341 RW_ENTER_WRITER(&hxgep->filter_lock);
344 if (hxgep->hash_filter == NULL) {
347 hxgep->hash_filter = KMEM_ZALLOC(sizeof (hash_filter_t),
351 hash_filter = hxgep->hash_filter;
367 (void) hpi_pfc_set_l2_hash(hxgep->hpi_reg_handle, B_FALSE);
368 (void) hxge_pfc_load_hash_table(hxgep);
369 (void) hpi_pfc_set_l2_hash(hxgep->hpi_reg_handle, B_TRUE);
372 RW_EXIT(&hxgep->filter_lock);
374 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_add_mcast_addr"));
378 RW_EXIT(&hxgep->filter_lock);
379 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "hxge_add_mcast_addr: "
389 hxge_del_mcast_addr(p_hxge_t hxgep, struct ether_addr *addrp)
398 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_del_mcast_addr"));
399 RW_ENTER_WRITER(&hxgep->filter_lock);
401 if (hxgep->hash_filter == NULL) {
404 RW_EXIT(&hxgep->filter_lock);
405 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_del_mcast_addr"));
409 hash_filter = hxgep->hash_filter;
423 hxgep->hash_filter = NULL;
427 (void) hpi_pfc_set_l2_hash(hxgep->hpi_reg_handle, B_FALSE);
428 (void) hxge_pfc_load_hash_table(hxgep);
431 if (hxgep->hash_filter != NULL)
432 (void) hpi_pfc_set_l2_hash(hxgep->hpi_reg_handle,
436 RW_EXIT(&hxgep->filter_lock);
437 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_del_mcast_addr"));
441 RW_EXIT(&hxgep->filter_lock);
442 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "hxge_del_mcast_addr: "
449 hxge_pfc_clear_mac_address(p_hxge_t hxgep, uint32_t slot)
453 status = hpi_pfc_clear_mac_address(hxgep->hpi_reg_handle, slot);
461 hxge_pfc_set_mac_address(p_hxge_t hxgep, uint32_t slot,
471 if (hxgep->hxge_hw_p == NULL) {
472 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
488 handle = hxgep->hpi_reg_handle;
492 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
502 hxge_pfc_num_macs_get(p_hxge_t hxgep, uint8_t *nmacs)
510 hxge_pfc_set_hash(p_hxge_t hxgep, uint32_t seed)
516 HXGE_DEBUG_MSG((hxgep, PFC_CTL, " ==> hxge_pfc_set_hash"));
518 p_class_cfgp = (p_hxge_class_pt_cfg_t)&hxgep->class_config;
520 handle = hxgep->hpi_reg_handle;
524 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
529 HXGE_DEBUG_MSG((hxgep, PFC_CTL, " <== hxge_pfc_set_hash"));
535 hxge_pfc_config_tcam_enable(p_hxge_t hxgep)
541 handle = hxgep->hpi_reg_handle;
542 if (hxgep->hxge_hw_p == NULL) {
543 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
550 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
559 hxge_pfc_config_tcam_disable(p_hxge_t hxgep)
565 handle = hxgep->hpi_reg_handle;
566 if (hxgep->hxge_hw_p == NULL) {
567 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
574 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
583 hxge_cfg_tcam_ip_class_get(p_hxge_t hxgep, tcam_class_t class,
591 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_cfg_tcam_ip_class_get"));
594 handle = hxgep->hpi_reg_handle;
598 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
611 HXGE_DEBUG_MSG((hxgep, PFC_CTL, " ==> hxge_cfg_tcam_ip_class_get %x",
618 hxge_pfc_ip_class_config_get(p_hxge_t hxgep, tcam_class_t class,
624 HXGE_DEBUG_MSG((hxgep, PFC_CTL, " ==> hxge_pfc_ip_class_config_get"));
626 t_status = hxge_cfg_tcam_ip_class_get(hxgep, class, &t_class_config);
629 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
635 HXGE_DEBUG_MSG((hxgep, PFC_CTL, " hxge_pfc_ip_class_config tcam %x",
640 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_pfc_ip_class_config_get"));
645 hxge_pfc_config_init(p_hxge_t hxgep)
650 handle = hxgep->hpi_reg_handle;
651 if (hxgep->hxge_hw_p == NULL) {
652 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
660 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);
683 hxge_pfc_tcam_invalidate_all(p_hxge_t hxgep)
689 HXGE_DEBUG_MSG((hxgep, PFC_CTL,
691 handle = hxgep->hpi_reg_handle;
692 if ((hw_p = hxgep->hxge_hw_p) == NULL) {
693 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
702 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_pfc_tcam_invalidate_all"));
710 hxge_pfc_tcam_init(p_hxge_t hxgep)
715 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_pfc_tcam_init"));
716 handle = hxgep->hpi_reg_handle;
718 if (hxgep->hxge_hw_p == NULL) {
719 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
729 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "failed TCAM Disable\n"));
736 rs = hxge_pfc_tcam_invalidate_all(hxgep);
738 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "failed TCAM Disable\n"));
742 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_pfc_tcam_init"));
747 hxge_pfc_vlan_tbl_clear_all(p_hxge_t hxgep)
753 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_pfc_vlan_tbl_clear_all "));
755 handle = hxgep->hpi_reg_handle;
756 if ((hw_p = hxgep->hxge_hw_p) == NULL) {
757 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
767 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
772 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_pfc_vlan_tbl_clear_all "));
777 hxge_pfc_ip_class_config(p_hxge_t hxgep, tcam_class_t class, uint32_t config)
785 HXGE_DEBUG_MSG((hxgep, PFC_CTL, " ==> hxge_pfc_ip_class_config"));
786 p_class_cfgp = (p_hxge_class_pt_cfg_t)&hxgep->class_config;
794 handle = hxgep->hpi_reg_handle;
815 HXGE_DEBUG_MSG((hxgep, PFC_CTL,
821 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_pfc_ip_class_config"));
826 hxge_pfc_ip_class_config_all(p_hxge_t hxgep)
832 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_pfc_ip_class_config_all"));
841 class_config = hxgep->class_config.class_cfg[cl];
842 status = hxge_pfc_ip_class_config(hxgep, cl, class_config);
844 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
850 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_pfc_ip_class_config_all"));
855 hxge_pfc_update_hw(p_hxge_t hxgep)
871 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_pfc_update_hw"));
872 p_class_cfgp = (p_hxge_class_pt_cfg_t)&hxgep->class_config;
873 handle = hxgep->hpi_reg_handle;
875 status = hxge_pfc_set_hash(hxgep, p_class_cfgp->init_hash);
877 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "hxge_pfc_set_hash Failed"));
898 pa = (p_hxge_param_t)&hxgep->param_arr[param_implicit_vlan_id];
911 HXGE_DEBUG_MSG((hxgep, PFC_CTL,
920 status = hxge_pfc_ip_class_config_all(hxgep);
922 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
931 hxge_pfc_hw_reset(p_hxge_t hxgep)
935 HXGE_DEBUG_MSG((hxgep, PFC_CTL, " ==> hxge_pfc_hw_reset"));
937 status = hxge_pfc_config_init(hxgep);
939 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
944 status = hxge_pfc_tcam_init(hxgep);
946 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "failed TCAM init."));
953 status = hxge_pfc_vlan_tbl_clear_all(hxgep);
955 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
959 hxgep->classifier.state |= HXGE_PFC_HW_RESET;
961 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_pfc_hw_reset"));
967 hxge_classify_init_hw(p_hxge_t hxgep)
971 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_classify_init_hw"));
973 if (hxgep->classifier.state & HXGE_PFC_HW_INIT) {
974 HXGE_DEBUG_MSG((hxgep, PFC_CTL,
980 status = hxge_pfc_update_hw(hxgep);
982 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
987 status = hxge_tcam_default_config(hxgep);
989 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
994 hxgep->classifier.state |= HXGE_PFC_HW_INIT;
996 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_classify_init_hw"));
1002 hxge_classify_init_sw(p_hxge_t hxgep)
1007 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_classify_init_sw"));
1008 classify_ptr = &hxgep->classifier;
1011 HXGE_DEBUG_MSG((hxgep, PFC_CTL,
1024 hxgep->classifier.tcam_location = 0;
1027 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_classify_init_sw"));
1033 hxge_classify_exit_sw(p_hxge_t hxgep)
1039 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_classify_exit_sw"));
1040 classify_ptr = &hxgep->classifier;
1047 hxgep->classifier.state = NULL;
1049 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_classify_exit_sw"));
1056 hxge_pfc_handle_sys_errors(p_hxge_t hxgep)
1065 p_hxge_t hxgep = (p_hxge_t)arg2;
1077 "<== hxge_pfc_intr: hxgep $%p ldvp $%p", hxgep, ldvp));
1081 if (arg2 == NULL || (void *) ldvp->hxgep != arg2) {
1082 hxgep = ldvp->hxgep;
1085 handle = hxgep->hpi_reg_handle;
1086 statsp = (p_hxge_pfc_stats_t)&hxgep->statsp->pfc_stats;
1097 HXGE_ERROR_MSG((hxgep, INT_CTL, "PFC pkt_drop"));
1125 HXGE_ERROR_MSG((hxgep,
1137 HXGE_ERROR_MSG((hxgep, INT_CTL,
1170 hxge_pfc_mac_addrs_get(p_hxge_t hxgep)
1174 hpi_handle_t handle = HXGE_DEV_HPI_HANDLE(hxgep);
1177 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_pfc_mac_addr_get"));
1182 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1187 hxge_pfc_get_next_mac_addr(mac_addr, &hxgep->factaddr);
1188 HXGE_ERROR_MSG((hxgep, PFC_CTL, "MAC Addr(0): %x:%x:%x:%x:%x:%x\n",
1193 HXGE_DEBUG_MSG((hxgep, CFG_CTL, "<== hxge_pfc_mac_addr_get, "
1229 hxge_pfc_load_hash_table(p_hxge_t hxgep)
1236 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "==> hxge_pfc_load_hash_table\n"));
1237 handle = hxgep->hpi_reg_handle;
1242 hash_filter = hxgep->hash_filter;
1255 HXGE_DEBUG_MSG((hxgep, PFC_CTL, "<== hxge_pfc_load_hash_table\n"));