Lines Matching defs:hxgep
97 static hxge_status_t hxge_map_regs(p_hxge_t hxgep);
98 static void hxge_unmap_regs(p_hxge_t hxgep);
100 static hxge_status_t hxge_add_intrs(p_hxge_t hxgep);
101 static void hxge_remove_intrs(p_hxge_t hxgep);
102 static hxge_status_t hxge_add_intrs_adv(p_hxge_t hxgep);
105 static void hxge_intrs_enable(p_hxge_t hxgep);
106 static void hxge_intrs_disable(p_hxge_t hxgep);
144 static hxge_status_t hxge_mac_register(p_hxge_t hxgep);
154 static int hxge_set_priv_prop(p_hxge_t hxgep, const char *pr_name,
156 static int hxge_get_priv_prop(p_hxge_t hxgep, const char *pr_name,
160 static void hxge_msix_init(p_hxge_t hxgep);
185 extern hxge_status_t hxge_pfc_set_default_mac_addr(p_hxge_t hxgep);
227 extern void hxge_fm_init(p_hxge_t hxgep, ddi_device_acc_attr_t *reg_attr,
229 extern void hxge_fm_fini(p_hxge_t hxgep);
391 p_hxge_t hxgep = NULL;
396 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_attach"));
406 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_ATTACH"));
410 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_RESUME"));
411 hxgep = (p_hxge_t)ddi_get_soft_state(hxge_list, instance);
412 if (hxgep == NULL) {
416 if (hxgep->dip != dip) {
420 if (hxgep->suspended == DDI_PM_SUSPEND) {
421 status = ddi_dev_is_needed(hxgep->dip, 0, 1);
423 (void) hxge_resume(hxgep);
428 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_PM_RESUME"));
429 hxgep = (p_hxge_t)ddi_get_soft_state(hxge_list, instance);
430 if (hxgep == NULL) {
434 if (hxgep->dip != dip) {
438 (void) hxge_resume(hxgep);
442 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing unknown"));
449 HXGE_ERROR_MSG((hxgep, DDI_CTL,
454 hxgep = ddi_get_soft_state(hxge_list, instance);
455 if (hxgep == NULL) {
457 HXGE_ERROR_MSG((hxgep, DDI_CTL,
462 hxgep->drv_state = 0;
463 hxgep->dip = dip;
464 hxgep->instance = instance;
465 hxgep->p_dip = ddi_get_parent(dip);
466 hxgep->hxge_debug_level = hxge_debug_level;
472 (void) hxge_pfc_num_macs_get(hxgep, &hxgep->mmac.total);
473 hxgep->mmac.available = hxgep->mmac.total;
474 for (i = 0; i < hxgep->mmac.total; i++) {
475 hxgep->mmac.addrs[i].set = B_FALSE;
476 hxgep->mmac.addrs[i].primary = B_FALSE;
479 hxge_fm_init(hxgep, &hxge_dev_reg_acc_attr, &hxge_dev_desc_dma_acc_attr,
482 status = hxge_map_regs(hxgep);
484 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "hxge_map_regs failed"));
488 status = hxge_init_common_dev(hxgep);
490 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
498 hxge_init_param(hxgep);
506 hxge_init_statsp(hxgep);
508 status = hxge_setup_mutexes(hxgep);
510 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "set mutex failed"));
515 hxge_msix_init(hxgep);
517 status = hxge_get_config_properties(hxgep);
519 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "get_hw create failed"));
526 hxge_setup_kstats(hxgep);
527 hxge_setup_param(hxgep);
529 status = hxge_setup_system_dma_pages(hxgep);
531 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "set dma page failed"));
535 hxge_hw_id_init(hxgep);
536 hxge_hw_init_niu_common(hxgep);
538 status = hxge_setup_dev(hxgep);
540 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "set dev failed"));
544 status = hxge_add_intrs(hxgep);
546 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "add_intr failed"));
553 hxge_intrs_enable(hxgep);
555 if ((status = hxge_mac_register(hxgep)) != HXGE_OK) {
556 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
560 mac_link_update(hxgep->mach, LINK_STATE_UNKNOWN);
562 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "registered to mac (instance %d)",
568 hxge_unattach(hxgep);
575 hxge_destroy_param(hxgep);
580 hxge_destroy_kstats(hxgep);
583 if (hxgep->hxge_hw_p) {
584 hxge_uninit_common_dev(hxgep);
585 hxgep->hxge_hw_p = NULL;
591 hxge_unmap_regs(hxgep);
593 hxge_fm_fini(hxgep);
596 ddi_soft_state_free(hxge_list, hxgep->instance);
601 hxgep = NULL;
604 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_attach status = 0x%08x",
615 p_hxge_t hxgep = NULL;
617 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_detach"));
619 hxgep = ddi_get_soft_state(hxge_list, instance);
620 if (hxgep == NULL) {
627 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_DETACH"));
631 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_PM_SUSPEND"));
632 hxgep->suspended = DDI_PM_SUSPEND;
633 hxge_suspend(hxgep);
637 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_SUSPEND"));
638 if (hxgep->suspended != DDI_PM_SUSPEND) {
639 hxgep->suspended = DDI_SUSPEND;
640 hxge_suspend(hxgep);
655 hxgep->suspended = cmd;
657 if (hxgep->mach && (status = mac_unregister(hxgep->mach)) != 0) {
658 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
662 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
665 hxge_unattach(hxgep);
666 hxgep = NULL;
669 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_detach status = 0x%08X",
676 hxge_unattach(p_hxge_t hxgep)
678 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_unattach"));
680 if (hxgep == NULL || hxgep->dev_regs == NULL) {
684 if (hxgep->hxge_hw_p) {
685 hxge_uninit_common_dev(hxgep);
686 hxgep->hxge_hw_p = NULL;
689 if (hxgep->hxge_timerid) {
690 hxge_stop_timer(hxgep, hxgep->hxge_timerid);
691 hxgep->hxge_timerid = 0;
695 hxge_intrs_disable(hxgep);
698 hxge_remove_intrs(hxgep);
701 hxge_destroy_dev(hxgep);
704 hxge_destroy_param(hxgep);
707 hxge_destroy_kstats(hxgep);
712 if (hxgep->dip) {
713 HXGE_DEBUG_MSG((hxgep, OBP_CTL,
715 (void) ddi_prop_remove_all(hxgep->dip);
722 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, 0x0000001E);
728 hxge_unmap_regs(hxgep);
730 hxge_fm_fini(hxgep);
733 hxge_destroy_mutexes(hxgep);
738 ddi_soft_state_free(hxge_list, hxgep->instance);
744 hxge_map_regs(p_hxge_t hxgep)
757 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_map_regs"));
759 if (ddi_dev_nregs(hxgep->dip, &nregs) != DDI_SUCCESS)
762 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "hxge_map_regs: nregs: %d", nregs));
764 hxgep->dev_regs = NULL;
770 (void) ddi_dev_regsize(hxgep->dip, 0, ®size);
771 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
774 ddi_status = ddi_regs_map_setup(hxgep->dip, 0,
778 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
783 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
788 (void) ddi_dev_regsize(hxgep->dip, 1, ®size);
789 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
793 ddi_status = ddi_regs_map_setup(hxgep->dip, 1,
798 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
804 (void) ddi_dev_regsize(hxgep->dip, 2, ®size);
805 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
808 ddi_status = ddi_regs_map_setup(hxgep->dip, 2,
813 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
818 hxgep->dev_regs = dev_regs;
820 HPI_PCI_ACC_HANDLE_SET(hxgep, dev_regs->hxge_pciregh);
821 HPI_PCI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_pciregp);
822 HPI_MSI_ACC_HANDLE_SET(hxgep, dev_regs->hxge_msix_regh);
823 HPI_MSI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_msix_regp);
825 HPI_ACC_HANDLE_SET(hxgep, dev_regs->hxge_regh);
826 HPI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_regp);
828 HPI_REG_ACC_HANDLE_SET(hxgep, dev_regs->hxge_regh);
829 HPI_REG_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_regp);
831 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "hxge_map_reg: hardware addr 0x%0llx "
852 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "Freeing register set memory"));
858 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_map_regs"));
863 hxge_unmap_regs(p_hxge_t hxgep)
865 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_unmap_regs"));
866 if (hxgep->dev_regs) {
867 if (hxgep->dev_regs->hxge_pciregh) {
868 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
870 ddi_regs_map_free(&hxgep->dev_regs->hxge_pciregh);
871 hxgep->dev_regs->hxge_pciregh = NULL;
874 if (hxgep->dev_regs->hxge_regh) {
875 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
877 ddi_regs_map_free(&hxgep->dev_regs->hxge_regh);
878 hxgep->dev_regs->hxge_regh = NULL;
881 if (hxgep->dev_regs->hxge_msix_regh) {
882 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
884 ddi_regs_map_free(&hxgep->dev_regs->hxge_msix_regh);
885 hxgep->dev_regs->hxge_msix_regh = NULL;
887 kmem_free(hxgep->dev_regs, sizeof (dev_regs_t));
888 hxgep->dev_regs = NULL;
890 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_unmap_regs"));
894 hxge_setup_mutexes(p_hxge_t hxgep)
899 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_setup_mutexes"));
904 ddi_status = ddi_get_iblock_cookie(hxgep->dip, 0,
905 &hxgep->interrupt_cookie);
908 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
916 MUTEX_INIT(hxgep->genlock, NULL,
917 MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
918 MUTEX_INIT(&hxgep->vmac_lock, NULL,
919 MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
920 MUTEX_INIT(&hxgep->ouraddr_lock, NULL,
921 MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
922 RW_INIT(&hxgep->filter_lock, NULL,
923 RW_DRIVER, (void *) hxgep->interrupt_cookie);
924 MUTEX_INIT(&hxgep->pio_lock, NULL,
925 MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
926 MUTEX_INIT(&hxgep->timeout.lock, NULL,
927 MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
930 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
940 hxge_destroy_mutexes(p_hxge_t hxgep)
942 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_destroy_mutexes"));
943 RW_DESTROY(&hxgep->filter_lock);
944 MUTEX_DESTROY(&hxgep->vmac_lock);
945 MUTEX_DESTROY(&hxgep->ouraddr_lock);
946 MUTEX_DESTROY(hxgep->genlock);
947 MUTEX_DESTROY(&hxgep->pio_lock);
948 MUTEX_DESTROY(&hxgep->timeout.lock);
955 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_destroy_mutexes"));
959 hxge_init(p_hxge_t hxgep)
963 HXGE_DEBUG_MSG((hxgep, STR_CTL, "==> hxge_init"));
965 if (hxgep->drv_state & STATE_HW_INITIALIZED) {
973 status = hxge_alloc_mem_pool(hxgep);
975 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "alloc mem failed\n"));
982 status = hxge_init_txdma_channels(hxgep);
984 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init txdma failed\n"));
991 status = hxge_init_rxdma_channels(hxgep);
993 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init rxdma failed\n"));
1000 status = hxge_classify_init(hxgep);
1002 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init classify failed\n"));
1009 status = hxge_vmac_init(hxgep);
1011 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init MAC failed\n"));
1016 status = hxge_pfc_set_default_mac_addr(hxgep);
1018 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1026 hxge_intr_hw_enable(hxgep);
1027 hxgep->drv_state |= STATE_HW_INITIALIZED;
1032 hxge_uninit_rxdma_channels(hxgep);
1034 hxge_uninit_txdma_channels(hxgep);
1036 hxge_free_mem_pool(hxgep);
1038 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1044 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_init status = 0x%08x",
1051 hxge_start_timer(p_hxge_t hxgep, fptrv_t func, int msec)
1053 if ((hxgep->suspended == 0) || (hxgep->suspended == DDI_RESUME)) {
1054 return (timeout(func, (caddr_t)hxgep,
1062 hxge_stop_timer(p_hxge_t hxgep, timeout_id_t timerid)
1070 hxge_uninit(p_hxge_t hxgep)
1072 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_uninit"));
1074 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) {
1075 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
1077 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_uninit"));
1082 if (hxgep->hxge_timerid) {
1083 hxge_stop_timer(hxgep, hxgep->hxge_timerid);
1084 hxgep->hxge_timerid = 0;
1087 (void) hxge_intr_hw_disable(hxgep);
1090 (void) hxge_rx_vmac_disable(hxgep);
1093 (void) hxge_classify_uninit(hxgep);
1096 (void) hxge_txdma_hw_mode(hxgep, HXGE_DMA_STOP);
1097 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP);
1099 hxge_uninit_txdma_channels(hxgep);
1100 hxge_uninit_rxdma_channels(hxgep);
1103 (void) hxge_tx_vmac_disable(hxgep);
1105 hxge_free_mem_pool(hxgep);
1107 hxgep->drv_state &= ~STATE_HW_INITIALIZED;
1109 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_uninit"));
1115 hxge_debug_msg(p_hxge_t hxgep, uint64_t level, char *fmt, ...)
1124 debug_level = (hxgep == NULL) ? hxge_debug_level :
1125 hxgep->hxge_debug_level;
1149 if (hxgep == NULL) {
1153 instance = hxgep->instance;
1206 hxge_suspend(p_hxge_t hxgep)
1208 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_suspend"));
1215 MUTEX_ENTER(&hxgep->timeout.lock);
1216 if (hxgep->timeout.id)
1217 (void) untimeout(hxgep->timeout.id);
1218 MUTEX_EXIT(&hxgep->timeout.lock);
1220 hxge_intrs_disable(hxgep);
1221 hxge_destroy_dev(hxgep);
1223 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_suspend"));
1227 hxge_resume(p_hxge_t hxgep)
1231 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_resume"));
1232 hxgep->suspended = DDI_RESUME;
1234 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_START);
1235 (void) hxge_txdma_hw_mode(hxgep, HXGE_DMA_START);
1237 (void) hxge_rx_vmac_enable(hxgep);
1238 (void) hxge_tx_vmac_enable(hxgep);
1240 hxge_intrs_enable(hxgep);
1242 hxgep->suspended = 0;
1248 MUTEX_ENTER(&hxgep->timeout.lock);
1249 hxgep->timeout.id = timeout(hxge_link_poll, (void *)hxgep,
1250 hxgep->timeout.ticks);
1251 MUTEX_EXIT(&hxgep->timeout.lock);
1253 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
1260 hxge_setup_dev(p_hxge_t hxgep)
1264 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_setup_dev"));
1266 status = hxge_link_init(hxgep);
1267 if (fm_check_acc_handle(hxgep->dev_regs->hxge_regh) != DDI_FM_OK) {
1268 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1274 HXGE_DEBUG_MSG((hxgep, MAC_CTL,
1280 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
1287 hxge_destroy_dev(p_hxge_t hxgep)
1289 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_destroy_dev"));
1291 (void) hxge_hw_stop(hxgep);
1293 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_destroy_dev"));
1297 hxge_setup_system_dma_pages(p_hxge_t hxgep)
1305 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_setup_system_dma_pages"));
1307 hxgep->sys_page_sz = ddi_ptob(hxgep->dip, (ulong_t)1);
1308 iommu_pagesize = dvma_pagesize(hxgep->dip);
1310 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
1313 hxgep->sys_page_sz, ddi_ptob(hxgep->dip, (ulong_t)1),
1314 hxgep->rx_default_block_size, iommu_pagesize));
1317 if (hxgep->sys_page_sz == iommu_pagesize) {
1320 hxgep->sys_page_sz = 0x2000;
1322 if (hxgep->sys_page_sz > iommu_pagesize)
1323 hxgep->sys_page_sz = iommu_pagesize;
1327 hxgep->sys_page_mask = ~(hxgep->sys_page_sz - 1);
1329 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
1332 hxgep->sys_page_sz, ddi_ptob(hxgep->dip, (ulong_t)1),
1333 hxgep->rx_default_block_size, hxgep->sys_page_mask));
1335 switch (hxgep->sys_page_sz) {
1337 hxgep->sys_page_sz = 0x1000;
1338 hxgep->sys_page_mask = ~(hxgep->sys_page_sz - 1);
1339 hxgep->rx_default_block_size = 0x1000;
1340 hxgep->rx_bksize_code = RBR_BKSIZE_4K;
1343 hxgep->rx_default_block_size = 0x1000;
1344 hxgep->rx_bksize_code = RBR_BKSIZE_4K;
1347 hxgep->rx_default_block_size = 0x2000;
1348 hxgep->rx_bksize_code = RBR_BKSIZE_8K;
1352 hxge_rx_dma_attr.dma_attr_align = hxgep->sys_page_sz;
1353 hxge_tx_dma_attr.dma_attr_align = hxgep->sys_page_sz;
1358 ddi_status = ddi_dma_alloc_handle(hxgep->dip, &hxge_tx_dma_attr,
1359 DDI_DMA_DONTWAIT, 0, &hxgep->dmasparehandle);
1361 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1366 ddi_status = ddi_dma_addr_bind_handle(hxgep->dmasparehandle, NULL,
1367 (caddr_t)hxgep->dmasparehandle, sizeof (hxgep->dmasparehandle),
1371 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1377 hxgep->sys_burst_sz = ddi_dma_burstsizes(hxgep->dmasparehandle);
1378 (void) ddi_dma_unbind_handle(hxgep->dmasparehandle);
1381 ddi_dma_free_handle(&hxgep->dmasparehandle);
1388 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
1395 hxge_alloc_mem_pool(p_hxge_t hxgep)
1399 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_alloc_mem_pool"));
1401 status = hxge_alloc_rx_mem_pool(hxgep);
1406 status = hxge_alloc_tx_mem_pool(hxgep);
1408 hxge_free_rx_mem_pool(hxgep);
1412 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_alloc_mem_pool"));
1417 hxge_free_mem_pool(p_hxge_t hxgep)
1419 HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_free_mem_pool"));
1421 hxge_free_rx_mem_pool(hxgep);
1422 hxge_free_tx_mem_pool(hxgep);
1424 HXGE_DEBUG_MSG((hxgep, MEM_CTL, "<== hxge_free_mem_pool"));
1428 hxge_alloc_rx_mem_pool(p_hxge_t hxgep)
1453 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_rx_mem_pool"));
1455 p_all_cfgp = (p_hxge_dma_pt_cfg_t)&hxgep->pt_config;
1460 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1511 rx_buf_alloc_size = (hxgep->rx_default_block_size *
1523 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_alloc_rx_mem_pool: "
1529 hxgep->hxge_port_rbr_size = hxge_port_rbr_size;
1530 hxgep->hxge_port_rcr_size = hxge_port_rcr_size;
1541 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
1548 status = hxge_alloc_rx_buf_dma(hxgep, st_rdc, &dma_buf_p[i],
1549 rx_buf_alloc_size, hxgep->rx_default_block_size,
1556 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
1571 if ((status = hxge_alloc_rx_cntl_dma(hxgep, st_rdc,
1577 if ((status = hxge_alloc_rx_cntl_dma(hxgep, st_rdc,
1583 if ((status = hxge_alloc_rx_cntl_dma(hxgep, st_rdc,
1598 hxgep->rx_buf_pool_p = dma_poolp;
1603 hxgep->rx_rbr_cntl_pool_p = dma_rbr_cntl_poolp;
1608 hxgep->rx_rcr_cntl_pool_p = dma_rcr_cntl_poolp;
1613 hxgep->rx_mbox_cntl_pool_p = dma_mbox_cntl_poolp;
1620 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1623 hxge_free_rx_cntl_dma(hxgep,
1625 hxge_free_rx_cntl_dma(hxgep,
1627 hxge_free_rx_cntl_dma(hxgep,
1629 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1632 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1638 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1641 hxge_free_rx_buf_dma(hxgep, (p_hxge_dma_common_t)dma_buf_p[i],
1644 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1658 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1665 hxge_free_rx_mem_pool(p_hxge_t hxgep)
1678 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_free_rx_mem_pool"));
1680 dma_poolp = hxgep->rx_buf_pool_p;
1682 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_free_rx_mem_pool "
1687 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p;
1690 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
1696 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p;
1699 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
1705 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p;
1708 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
1723 hxge_free_rx_buf_dma(hxgep, dma_buf_p[i], num_chunks[i]);
1727 hxge_free_rx_cntl_dma(hxgep, dma_rbr_cntl_p[i]);
1728 hxge_free_rx_cntl_dma(hxgep, dma_rcr_cntl_p[i]);
1729 hxge_free_rx_cntl_dma(hxgep, dma_mbox_cntl_p[i]);
1750 hxgep->rx_buf_pool_p = NULL;
1751 hxgep->rx_rbr_cntl_pool_p = NULL;
1752 hxgep->rx_rcr_cntl_pool_p = NULL;
1753 hxgep->rx_mbox_cntl_pool_p = NULL;
1755 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_free_rx_mem_pool"));
1759 hxge_alloc_rx_buf_dma(p_hxge_t hxgep, uint16_t dma_channel,
1769 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_rx_buf_dma"));
1774 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
1800 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
1805 status = hxge_dma_mem_alloc(hxgep, hxge_force_dma,
1811 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1816 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1827 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1834 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1846 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1854 hxge_free_rx_buf_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap,
1859 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
1863 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
1868 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_free_rx_buf_dma"));
1873 hxge_alloc_rx_cntl_dma(p_hxge_t hxgep, uint16_t dma_channel,
1879 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_rx_cntl_dma"));
1886 status = hxge_dma_mem_alloc(hxgep, hxge_force_dma,
1890 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1904 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
1912 hxge_free_rx_cntl_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap)
1914 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_free_rx_cntl_dma"));
1918 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_free_rx_cntl_dma"));
1922 hxge_alloc_tx_mem_pool(p_hxge_t hxgep)
1937 HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_alloc_tx_mem_pool"));
1939 p_all_cfgp = (p_hxge_dma_pt_cfg_t)&hxgep->pt_config;
1944 HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_alloc_tx_mem_pool: "
1945 "p_cfgp 0x%016llx start_tdc %d ndmas %d hxgep->max_tdcs %d",
1946 p_cfgp, p_cfgp->start_tdc, p_cfgp->max_tdcs, hxgep->max_tdcs));
1960 hxgep->hxge_port_tx_ring_size = hxge_tx_ring_size;
1989 status = hxge_alloc_tx_buf_dma(hxgep, st_tdc, &dma_buf_p[i],
2007 status = hxge_alloc_tx_cntl_dma(hxgep, st_tdc, &dma_cntl_p[j],
2023 hxgep->tx_buf_pool_p = dma_poolp;
2028 hxgep->tx_cntl_pool_p = dma_cntl_poolp;
2030 HXGE_DEBUG_MSG((hxgep, MEM_CTL,
2040 hxge_free_tx_cntl_dma(hxgep,
2048 hxge_free_tx_buf_dma(hxgep, (p_hxge_dma_common_t)dma_buf_p[i],
2059 HXGE_DEBUG_MSG((hxgep, MEM_CTL,
2066 hxge_alloc_tx_buf_dma(p_hxge_t hxgep, uint16_t dma_channel,
2076 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_tx_buf_dma"));
2102 status = hxge_dma_mem_alloc(hxgep, hxge_force_dma,
2108 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
2119 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2128 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
2137 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
2145 hxge_free_tx_buf_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap,
2150 HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_free_tx_buf_dma"));
2156 HXGE_DEBUG_MSG((hxgep, MEM_CTL, "<== hxge_free_tx_buf_dma"));
2161 hxge_alloc_tx_cntl_dma(p_hxge_t hxgep, uint16_t dma_channel,
2167 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_tx_cntl_dma"));
2174 status = hxge_dma_mem_alloc(hxgep, hxge_force_dma,
2178 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2192 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
2200 hxge_free_tx_cntl_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap)
2202 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_free_tx_cntl_dma"));
2206 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_free_tx_cntl_dma"));
2210 hxge_free_tx_mem_pool(p_hxge_t hxgep)
2219 HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_free_tx_mem_pool"));
2221 dma_poolp = hxgep->tx_buf_pool_p;
2223 HXGE_DEBUG_MSG((hxgep, MEM3_CTL,
2229 dma_cntl_poolp = hxgep->tx_cntl_pool_p;
2231 HXGE_DEBUG_MSG((hxgep, MEM3_CTL,
2244 hxge_free_tx_buf_dma(hxgep, dma_buf_p[i], num_chunks[i]);
2248 hxge_free_tx_cntl_dma(hxgep, dma_cntl_p[i]);
2263 hxgep->tx_buf_pool_p = NULL;
2264 hxgep->tx_cntl_pool_p = NULL;
2266 HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_free_tx_mem_pool"));
2271 hxge_dma_mem_alloc(p_hxge_t hxgep, dma_method_t method,
2283 ddi_status = ddi_dma_alloc_handle(hxgep->dip, dma_attrp,
2286 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2296 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
2304 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2317 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2330 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
2353 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_dma_mem_alloc: "
2410 p_hxge_t hxgep = (p_hxge_t)arg;
2412 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "==> hxge_m_start"));
2414 MUTEX_ENTER(hxgep->genlock);
2416 if (hxge_init(hxgep) != DDI_SUCCESS) {
2417 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2419 MUTEX_EXIT(hxgep->genlock);
2423 if (hxgep->hxge_mac_state != HXGE_MAC_STARTED) {
2427 hxgep->hxge_timerid = hxge_start_timer(hxgep,
2430 hxgep->hxge_mac_state = HXGE_MAC_STARTED;
2432 hxgep->timeout.link_status = 0;
2433 hxgep->timeout.report_link_status = B_TRUE;
2434 hxgep->timeout.ticks = drv_usectohz(2 * 1000000);
2437 MUTEX_ENTER(&hxgep->timeout.lock);
2438 hxgep->timeout.id = timeout(hxge_link_poll, (void *)hxgep,
2439 hxgep->timeout.ticks);
2440 MUTEX_EXIT(&hxgep->timeout.lock);
2443 MUTEX_EXIT(hxgep->genlock);
2445 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "<== hxge_m_start"));
2456 p_hxge_t hxgep = (p_hxge_t)arg;
2458 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "==> hxge_m_stop"));
2460 if (hxgep->hxge_timerid) {
2461 hxge_stop_timer(hxgep, hxgep->hxge_timerid);
2462 hxgep->hxge_timerid = 0;
2466 MUTEX_ENTER(&hxgep->timeout.lock);
2467 if (hxgep->timeout.id) {
2468 (void) untimeout(hxgep->timeout.id);
2469 hxgep->timeout.id = 0;
2471 hxge_link_update(hxgep, LINK_STATE_DOWN);
2472 MUTEX_EXIT(&hxgep->timeout.lock);
2474 MUTEX_ENTER(hxgep->genlock);
2476 hxge_uninit(hxgep);
2478 hxgep->hxge_mac_state = HXGE_MAC_STOPPED;
2480 MUTEX_EXIT(hxgep->genlock);
2482 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "<== hxge_m_stop"));
2488 p_hxge_t hxgep = (p_hxge_t)arg;
2491 HXGE_DEBUG_MSG((hxgep, MAC_CTL, "==> hxge_m_multicst: add %d", add));
2496 if (hxge_add_mcast_addr(hxgep, &addrp)) {
2497 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2502 if (hxge_del_mcast_addr(hxgep, &addrp)) {
2503 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2509 HXGE_DEBUG_MSG((hxgep, MAC_CTL, "<== hxge_m_multicst"));
2517 p_hxge_t hxgep = (p_hxge_t)arg;
2519 HXGE_DEBUG_MSG((hxgep, MAC_CTL, "==> hxge_m_promisc: on %d", on));
2521 if (hxge_set_promisc(hxgep, on)) {
2522 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2527 HXGE_DEBUG_MSG((hxgep, MAC_CTL, "<== hxge_m_promisc: on %d", on));
2535 p_hxge_t hxgep = (p_hxge_t)arg;
2541 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "==> hxge_m_ioctl"));
2548 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "==> hxge_m_ioctl: cmd 0x%08x", cmd));
2552 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "<== hxge_m_ioctl: invalid"));
2588 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2596 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "ND_GET command"));
2598 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "ND_SET command"));
2599 hxge_param_ioctl(hxgep, wq, mp, iocp);
2606 hxge_loopback_ioctl(hxgep, wq, mp, iocp);
2617 HXGE_DEBUG_MSG((hxgep, NEMO_CTL,
2619 hxge_hw_ioctl(hxgep, wq, mp, iocp);
2623 HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "<== hxge_m_ioctl"));
2631 p_hxge_t hxgep;
2637 hxgep = rhp->hxgep;
2642 ring = hxgep->tx_rings->rings[rhp->index];
2659 p_hxge_t hxgep;
2665 hxgep = rhp->hxgep;
2666 ring = hxgep->tx_rings->rings[rhp->index];
2678 p_hxge_t hxgep;
2685 hxgep = rhp->hxgep;
2690 ring = hxgep->rx_rcr_rings->rcr_rings[rhp->index];
2703 for (i = 0; i < hxgep->ldgvp->maxldvs; i++) {
2704 if ((hxgep->ldgvp->ldvp[i].is_rxdma == 1) &&
2705 (hxgep->ldgvp->ldvp[i].channel == rhp->index)) {
2706 ring->ldvp = &hxgep->ldgvp->ldvp[i];
2707 ring->ldgp = hxgep->ldgvp->ldvp[i].ldgp;
2724 p_hxge_t hxgep;
2730 hxgep = rhp->hxgep;
2731 ring = hxgep->rx_rcr_rings->rcr_rings[rhp->index];
2746 ASSERT(group->hxgep != NULL);
2747 ASSERT(group->hxgep->hxge_mac_state == HXGE_MAC_STARTED);
2749 MUTEX_ENTER(group->hxgep->genlock);
2751 MUTEX_EXIT(group->hxgep->genlock);
2761 ASSERT(group->hxgep != NULL);
2762 ASSERT(group->hxgep->hxge_mac_state == HXGE_MAC_STARTED);
2765 MUTEX_ENTER(group->hxgep->genlock);
2767 MUTEX_EXIT(group->hxgep->genlock);
2771 hxge_mmac_get_slot(p_hxge_t hxgep, int *slot)
2778 for (i = 0; i < hxgep->mmac.total; i++) {
2779 if (!hxgep->mmac.addrs[i].set) {
2789 hxge_mmac_set_addr(p_hxge_t hxgep, int slot, const uint8_t *addr)
2801 RW_ENTER_WRITER(&hxgep->filter_lock);
2802 status = hxge_pfc_set_mac_address(hxgep, slot, &eaddr);
2803 RW_EXIT(&hxgep->filter_lock);
2807 hxgep->mmac.addrs[slot].set = B_TRUE;
2808 bcopy(addr, hxgep->mmac.addrs[slot].addr, ETHERADDRL);
2809 hxgep->mmac.available--;
2811 hxgep->mmac.addrs[slot].primary = B_TRUE;
2817 hxge_mmac_find_addr(p_hxge_t hxgep, const uint8_t *addr, int *slot)
2821 for (i = 0; i < hxgep->mmac.total; i++) {
2822 if (hxgep->mmac.addrs[i].set) {
2823 result = memcmp(hxgep->mmac.addrs[i].addr,
2836 hxge_mmac_unset_addr(p_hxge_t hxgep, int slot)
2841 status = hxge_pfc_clear_mac_address(hxgep, slot);
2846 hxgep->mmac.addrs[slot].addr[i] = 0;
2848 hxgep->mmac.addrs[slot].set = B_FALSE;
2850 hxgep->mmac.addrs[slot].primary = B_FALSE;
2851 hxgep->mmac.available++;
2860 p_hxge_t hxgep = group->hxgep;
2865 MUTEX_ENTER(hxgep->genlock);
2870 if (hxge_mmac_get_slot(hxgep, &slot) != 0) {
2871 MUTEX_EXIT(hxgep->genlock);
2878 if (hxge_mmac_set_addr(hxgep, slot, mac_addr) != 0) {
2879 MUTEX_EXIT(hxgep->genlock);
2883 MUTEX_EXIT(hxgep->genlock);
2891 p_hxge_t hxgep = group->hxgep;
2896 MUTEX_ENTER(hxgep->genlock);
2898 if ((rv = hxge_mmac_find_addr(hxgep, mac_addr, &slot)) != 0) {
2899 MUTEX_EXIT(hxgep->genlock);
2903 if ((rv = hxge_mmac_unset_addr(hxgep, slot)) != 0) {
2904 MUTEX_EXIT(hxgep->genlock);
2908 MUTEX_EXIT(hxgep->genlock);
2916 p_hxge_t hxgep = arg;
2923 group = &hxgep->rx_groups[groupid];
2924 group->hxgep = hxgep;
2944 hxge_ring_get_htable_idx(p_hxge_t hxgep, mac_ring_type_t type, uint32_t channel)
2948 ASSERT(hxgep->ldgvp != NULL);
2952 for (i = 0; i < hxgep->ldgvp->maxldvs; i++) {
2953 if ((hxgep->ldgvp->ldvp[i].is_rxdma) &&
2954 (hxgep->ldgvp->ldvp[i].channel == channel)) {
2956 hxgep->ldgvp->ldvp[i].ldgp->htable_idx);
2962 for (i = 0; i < hxgep->ldgvp->maxldvs; i++) {
2963 if ((hxgep->ldgvp->ldvp[i].is_txdma) &&
2964 (hxgep->ldgvp->ldvp[i].channel == channel)) {
2966 hxgep->ldgvp->ldvp[i].ldgp->htable_idx);
2986 p_hxge_t hxgep = arg;
2988 ASSERT(hxgep != NULL);
2999 rhp = &hxgep->tx_ring_handles[index];
3000 rhp->hxgep = hxgep;
3009 intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
3010 htable_idx = hxge_ring_get_htable_idx(hxgep, type, index);
3025 rhp = &hxgep->rx_ring_handles[index];
3026 rhp->hxgep = hxgep;
3038 intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
3039 htable_idx = hxge_ring_get_htable_idx(hxgep, type, index);
3063 p_hxge_t hxgep = arg;
3076 MUTEX_ENTER(hxgep->genlock);
3094 MUTEX_EXIT(hxgep->genlock);
3138 hxge_t *hxgep = barg;
3143 HXGE_DEBUG_MSG((hxgep, DLADM_CTL, "==> hxge_m_setprop"));
3145 statsp = hxgep->statsp;
3146 MUTEX_ENTER(hxgep->genlock);
3153 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3155 MUTEX_EXIT(hxgep->genlock);
3185 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3192 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3196 if (new_framesize == hxgep->vmac.maxframesize) {
3201 if (hxgep->hxge_mac_state == HXGE_MAC_STARTED) {
3212 old_framesize = hxgep->vmac.maxframesize;
3213 hxgep->vmac.maxframesize = (uint16_t)new_framesize;
3215 if (hxge_vmac_set_framesize(hxgep)) {
3216 hxgep->vmac.maxframesize =
3222 err = mac_maxsdu_update(hxgep->mach, new_mtu);
3224 hxgep->vmac.maxframesize =
3226 (void) hxge_vmac_set_framesize(hxgep);
3229 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3231 new_mtu, hxgep->vmac.maxframesize));
3235 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3237 err = hxge_set_priv_prop(hxgep, pr_name, pr_valsize,
3246 MUTEX_EXIT(hxgep->genlock);
3248 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3258 hxge_t *hxgep = barg;
3259 p_hxge_stats_t statsp = hxgep->statsp;
3265 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3271 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3320 err = hxge_get_priv_prop(hxgep, pr_name, pr_valsize,
3329 HXGE_DEBUG_MSG((hxgep, DLADM_CTL, "<== hxge_m_getprop"));
3390 hxge_set_priv_prop(p_hxge_t hxgep, const char *pr_name, uint_t pr_valsize,
3393 p_hxge_param_t param_arr = hxgep->param_arr;
3396 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3405 err = hxge_param_rx_intr_time(hxgep, NULL, NULL,
3408 err = hxge_param_rx_intr_pkts(hxgep, NULL, NULL,
3413 err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3416 err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3419 err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3422 err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3425 err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3428 err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3431 err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3434 err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3440 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3447 hxge_get_priv_prop(p_hxge_t hxgep, const char *pr_name, uint_t pr_valsize,
3450 p_hxge_param_t param_arr = hxgep->param_arr;
3456 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3461 value = hxgep->intr_timeout;
3463 value = hxgep->intr_threshold;
3467 err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
3472 err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
3477 err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
3482 err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
3487 err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
3492 err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
3497 err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
3502 err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
3521 HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3624 hxge_add_intrs(p_hxge_t hxgep)
3631 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs"));
3633 hxgep->hxge_intr_type.intr_registered = B_FALSE;
3634 hxgep->hxge_intr_type.intr_enabled = B_FALSE;
3635 hxgep->hxge_intr_type.msi_intx_cnt = 0;
3636 hxgep->hxge_intr_type.intr_added = 0;
3637 hxgep->hxge_intr_type.niu_msi_enable = B_FALSE;
3638 hxgep->hxge_intr_type.intr_type = 0;
3641 hxgep->hxge_intr_type.niu_msi_enable = B_TRUE;
3645 if ((ddi_status = ddi_intr_get_supported_types(hxgep->dip, &intr_types))
3647 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "<== hxge_add_intrs: "
3653 hxgep->hxge_intr_type.intr_types = intr_types;
3655 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs: "
3667 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs: "
3672 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs: "
3676 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3681 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3686 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs: "
3694 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3699 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3704 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3710 hxgep->hxge_intr_type.intr_type = type;
3713 hxgep->hxge_intr_type.niu_msi_enable) {
3714 if ((status = hxge_add_intrs_adv(hxgep)) != DDI_SUCCESS) {
3715 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3721 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_add_intrs: "
3723 hxgep->hxge_intr_type.intr_registered = B_TRUE;
3725 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
3733 if (!hxgep->hxge_intr_type.intr_registered) {
3734 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3739 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs"));
3746 hxge_add_intrs_adv(p_hxge_t hxgep)
3752 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv"));
3754 intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
3757 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv: type 0x%x",
3763 status = hxge_add_intrs_adv_type(hxgep, intr_type);
3767 status = hxge_add_intrs_adv_type_fix(hxgep, intr_type);
3775 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs_adv"));
3782 hxge_add_intrs_adv_type(p_hxge_t hxgep, uint32_t int_type)
3784 dev_info_t *dip = hxgep->dip;
3798 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv_type"));
3800 intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
3804 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3812 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3818 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3824 nrequest = hxge_create_msi_property(hxgep);
3827 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3847 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3852 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3864 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3870 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3876 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3888 status = hxge_ldgv_init(hxgep, &nactual, &nrequired);
3890 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3902 ldgp = hxgep->ldgvp->ldgp;
3903 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3914 arg2 = hxgep;
3917 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3923 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3928 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3935 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3949 (void) hxge_ldgv_uninit(hxgep);
3959 HXGE_DEBUG_MSG((hxgep, INT_CTL,
3964 (void) hxge_intr_ldgv_init(hxgep);
3966 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs_adv_type"));
3973 hxge_add_intrs_adv_type_fix(p_hxge_t hxgep, uint32_t int_type)
3975 dev_info_t *dip = hxgep->dip;
3988 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv_type_fix"));
3989 intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
3993 HXGE_DEBUG_MSG((hxgep, INT_CTL,
4001 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
4007 HXGE_DEBUG_MSG((hxgep, INT_CTL,
4018 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
4026 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
4038 status = hxge_ldgv_init(hxgep, &nactual, &nrequired);
4040 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
4052 ldgp = hxgep->ldgvp->ldgp;
4056 arg2 = hxgep;
4059 HXGE_DEBUG_MSG((hxgep, INT_CTL,
4066 HXGE_DEBUG_MSG((hxgep, INT_CTL,
4077 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
4090 (void) hxge_ldgv_uninit(hxgep);
4101 status = hxge_intr_ldgv_init(hxgep);
4103 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs_adv_type_fix"));
4110 hxge_remove_intrs(p_hxge_t hxgep)
4115 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_remove_intrs"));
4116 intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
4118 HXGE_DEBUG_MSG((hxgep, INT_CTL,
4123 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_remove_intrs:advanced"));
4142 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
4157 (void) hxge_ldgv_uninit(hxgep);
4159 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_remove_intrs"));
4164 hxge_intrs_enable(p_hxge_t hxgep)
4170 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_enable"));
4172 intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
4175 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "<== hxge_intrs_enable: "
4181 HXGE_DEBUG_MSG((hxgep, INT_CTL,
4189 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_enable "
4195 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_enable "
4205 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intrs_enable"));
4210 hxge_intrs_disable(p_hxge_t hxgep)
4215 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_disable"));
4217 intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
4220 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intrs_disable: "
4235 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intrs_disable"));
4239 hxge_mac_register(p_hxge_t hxgep)
4244 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_mac_register"));
4250 macp->m_driver = hxgep;
4251 macp->m_dip = hxgep->dip;
4252 macp->m_src_addr = hxgep->ouraddr.ether_addr_octet;
4255 macp->m_max_sdu = hxgep->vmac.maxframesize - MTU_TO_FRAME_SIZE;
4260 HXGE_DEBUG_MSG((hxgep, DDI_CTL,
4269 status = mac_register(macp, &hxgep->mach);
4275 status, hxgep->instance);
4279 HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_mac_register success "
4280 "(instance %d)", hxgep->instance));
4286 hxge_init_common_dev(p_hxge_t hxgep)
4291 HXGE_DEBUG_MSG((hxgep, MOD_CTL, "==> hxge_init_common_dev"));
4293 p_dip = hxgep->p_dip;
4300 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4304 hxgep->hxge_hw_p = hw_p;
4306 hw_p->hxge_p = hxgep;
4307 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4316 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4321 hxgep->hxge_hw_p = hw_p;
4323 hw_p->hxge_p = hxgep;
4333 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4335 HXGE_DEBUG_MSG((hxgep, MOD_CTL, "<== hxge_init_common_dev"));
4341 hxge_uninit_common_dev(p_hxge_t hxgep)
4346 HXGE_DEBUG_MSG((hxgep, MOD_CTL, "==> hxge_uninit_common_dev"));
4347 if (hxgep->hxge_hw_p == NULL) {
4348 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4357 if (hxgep->hxge_hw_p == hw_p && p_dip == hxgep->p_dip &&
4358 hxgep->hxge_hw_p->magic == HXGE_MAGIC &&
4360 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4365 hxgep->hxge_hw_p = NULL;
4374 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4380 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4388 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4406 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4409 HXGE_DEBUG_MSG((hxgep, MOD_CTL, "<= hxge_uninit_common_dev"));
4419 p_hxge_t hxgep = (p_hxge_t)arg;
4422 hxge_timeout *to = &hxgep->timeout;
4424 handle = HXGE_DEV_HPI_HANDLE(hxgep);
4433 hxge_link_update(hxgep, LINK_STATE_UP);
4435 hxge_link_update(hxgep, LINK_STATE_DOWN);
4446 hxge_link_update(p_hxge_t hxgep, link_state_t state)
4448 p_hxge_stats_t statsp = (p_hxge_stats_t)hxgep->statsp;
4450 mac_link_update(hxgep->mach, state);
4463 hxge_msix_init(p_hxge_t hxgep)
4480 HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16, data0);
4481 HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 4, data1);
4482 HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 8, data2);
4483 HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 12, 0);
4488 HXGE_REG_RD32(hxgep->hpi_msi_handle, i * 16, &msix_entry0);
4489 HXGE_REG_RD32(hxgep->hpi_msi_handle, i * 16 + 4, &msix_entry1);
4490 HXGE_REG_RD32(hxgep->hpi_msi_handle, i * 16 + 8, &msix_entry2);
4491 HXGE_REG_RD32(hxgep->hpi_msi_handle, i * 16 + 12, &msix_entry3);
4500 hxge_create_msi_property(p_hxge_t hxgep)
4505 HXGE_DEBUG_MSG((hxgep, MOD_CTL, "==>hxge_create_msi_property"));
4507 (void) ddi_prop_create(DDI_DEV_T_NONE, hxgep->dip,
4520 HXGE_DEBUG_MSG((hxgep, MOD_CTL,
4522 ddi_prop_exists(DDI_DEV_T_NONE, hxgep->dip,
4525 HXGE_DEBUG_MSG((hxgep, MOD_CTL, "<==hxge_create_msi_property"));