Lines Matching defs:cfg
65 rdc_rx_cfg1_t cfg;
69 RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
71 while ((count--) && (cfg.bits.qst == 0)) {
73 RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
76 if (cfg.bits.qst == 0)
86 rdc_rx_cfg1_t cfg;
99 RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
100 cfg.bits.enable = 1;
101 RXDMA_REG_WRITE64(handle, RDC_RX_CFG1, rdc, cfg.value);
104 RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
106 while ((count--) && (cfg.bits.qst == 1)) {
108 RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
110 if (cfg.bits.qst == 1) {
116 RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
117 cfg.bits.enable = 0;
118 RXDMA_REG_WRITE64(handle, RDC_RX_CFG1, rdc, cfg.value);
132 cfg.value = 0;
133 cfg.bits.reset = 1;
134 RXDMA_REG_WRITE64(handle, RDC_RX_CFG1, rdc, cfg.value);
136 RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);
138 while ((count--) && (cfg.bits.qst == 0)) {
140 RXDMA_REG_READ64(handle, RDC_RX_CFG1, rdc, &cfg.value);