Lines Matching defs:stat
163 uint32_t stat;
201 stat = 0;
219 stat = mbx & OSC_INDEX_MASK;
222 sp = stat < MAX_OUTSTANDING_COMMANDS ?
223 ha->outstanding_cmds[stat] : NULL;
227 ha->outstanding_cmds[stat] =
271 if (stat == 0) {
344 while (((stat = RD32_IO_REG(ha, risc2host)) & RH_RISC_INT) &&
350 mbx = MSW(stat);
366 switch (stat & 0x1ff) {
421 stat = (stat & 0xffff0000) | MBA_CMPLT_1_16BIT;
422 ql_async_event(ha, stat, &isr_done_q,
427 stat = (stat & 0xffff0000) | MBA_CMPLT_1_32BIT;
428 ql_async_event(ha, stat, &isr_done_q,
433 stat = (stat & 0xffff0000) |
435 ql_async_event(ha, stat, &isr_done_q,
440 stat = (stat & 0xffff0000) | MBA_IP_COMPLETION;
441 ql_async_event(ha, stat, &isr_done_q,
446 stat = (stat & 0xffff0000) | MBA_IP_RECEIVE;
447 ql_async_event(ha, stat, &isr_done_q,
452 stat = (stat & 0xffff0000) | MBA_IP_BROADCAST;
453 ql_async_event(ha, stat, &isr_done_q,
458 stat = (stat & 0xffff0000) |
460 ql_async_event(ha, stat, &isr_done_q,
466 " interrupt, status=%xh\n", stat);
472 "update interrupt, status=%xh\n", stat);
477 ql_handle_uncommon_risc_intr(ha, stat,
557 * stat: interrupt status
563 ql_handle_uncommon_risc_intr(ql_adapter_state_t *ha, uint32_t stat,
570 if (stat & RH_RISC_PAUSED ||
579 ha->parity_stat_err != stat) {
581 "Pause Error - hccr=%xh, stat=%xh, count=%d",
582 ha->instance, hccr_reg, stat,
585 ha->parity_stat_err = stat;
612 stat, hccr_reg);