Cross Reference: /illumos-gate/usr/src/uts/common/io/fibre-channel/fca/oce/oce

Lines Matching defs:dev
37  * dev - software handle to the device
42 oce_setup_intr(struct oce_dev *dev)
53 	ret = ddi_intr_get_supported_types(dev->dip, &intr_types);
55 		oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
62 		dev->intr_type = DDI_INTR_TYPE_MSIX;
64 		nreqd = dev->rx_rings + 1;
67 		dev->intr_type = DDI_INTR_TYPE_FIXED;
72 	ret = ddi_intr_get_nintrs(dev->dip, dev->intr_type, &nsupported);
74 		oce_log(dev, CE_WARN, MOD_CONFIG,
80 	ret = ddi_intr_get_navail(dev->dip, dev->intr_type, &navail);
82 		oce_log(dev, CE_WARN, MOD_CONFIG,
98 	dev->hsize  = nreqd *  sizeof (ddi_intr_handle_t);
99 	dev->htable = kmem_zalloc(dev->hsize,  KM_NOSLEEP);
101 	if (dev->htable == NULL)
106 	ret = ddi_intr_alloc(dev->dip, dev->htable, dev->intr_type,
113 	dev->num_vectors = nallocd;
123 	ret = ddi_intr_get_pri(dev->htable[0], &dev->intr_pri);
129 	(void) ddi_intr_get_cap(dev->htable[0], &dev->intr_cap);
132 		dev->rx_rings = nallocd - 1;
134 		dev->rx_rings = 1;
140 	(void) oce_teardown_intr(dev);
141 	if ((dev->intr_type == DDI_INTR_TYPE_MSIX) &&
144 		oce_log(dev, CE_NOTE, MOD_CONFIG, "%s",
154  * dev - software handle to the device
159 oce_teardown_intr(struct oce_dev *dev)
164 	for (i = 0; i < dev->num_vectors; i++) {
165 		(void) ddi_intr_free(dev->htable[i]);
169 	kmem_free(dev->htable, dev->hsize);
170 	dev->htable = NULL;
178  * dev - software handle to the device
183 oce_setup_handlers(struct oce_dev *dev)
187 	for (i = 0; i < dev->num_vectors; i++) {
188 		ret = ddi_intr_add_handler(dev->htable[i], oce_isr,
189 		    (caddr_t)dev->eq[i], NULL);
191 			oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
194 				(void) ddi_intr_remove_handler(dev->htable[i]);
205  * dev - software handle to the device
210 oce_remove_handler(struct oce_dev *dev)
213 	for (nvec = 0; nvec < dev->num_vectors; nvec++) {
214 		(void) ddi_intr_remove_handler(dev->htable[nvec]);
219 oce_chip_ei(struct oce_dev *dev)
223 	reg =  OCE_CFG_READ32(dev, PCICFG_INTR_CTRL);
225 	OCE_CFG_WRITE32(dev, PCICFG_INTR_CTRL, reg);
231  * dev - software handle to the device
236 oce_ei(struct oce_dev *dev)
241 	if (dev->intr_cap & DDI_INTR_FLAG_BLOCK) {
242 		(void) ddi_intr_block_enable(dev->htable, dev->num_vectors);
245 		for (i = 0; i < dev->num_vectors; i++) {
246 			ret = ddi_intr_enable(dev->htable[i]);
249 					(void) ddi_intr_disable(dev->htable[i]);
254 	oce_chip_ei(dev);
258 oce_chip_di(struct oce_dev *dev)
262 	reg =  OCE_CFG_READ32(dev, PCICFG_INTR_CTRL);
264 	OCE_CFG_WRITE32(dev, PCICFG_INTR_CTRL, reg);
270  * dev - software handle to the device
275 oce_di(struct oce_dev *dev)
280 	oce_chip_di(dev);
281 	if (dev->intr_cap & DDI_INTR_FLAG_BLOCK) {
282 		(void) ddi_intr_block_disable(dev->htable, dev->num_vectors);
284 		for (i = 0; i < dev->num_vectors; i++) {
285 			ret = ddi_intr_disable(dev->htable[i]);
287 				oce_log(dev, CE_WARN, MOD_CONFIG,
311 	struct oce_dev  *dev;
317 	dev = eq->parent;
327 			oce_log(dev, CE_WARN, MOD_ISR,
334 		cq = dev->cq[cq_id];
347 	oce_arm_eq(dev, eq->eq_id, num_eqe, B_TRUE, B_TRUE);