Lines Matching defs:dev
40 extern int oce_destroy_q(struct oce_dev *dev, struct oce_mbx *mbx,
44 oce_map_regs(struct oce_dev *dev)
49 ASSERT(NULL != dev);
50 ASSERT(NULL != dev->dip);
53 ret = ddi_dev_nregs(dev->dip, &dev->num_bars);
55 oce_log(dev, CE_WARN, MOD_CONFIG,
62 ret = ddi_dev_regsize(dev->dip, OCE_DEV_CFG_BAR, &bar_size);
64 oce_log(dev, CE_WARN, MOD_CONFIG,
70 ret = ddi_regs_map_setup(dev->dip, OCE_DEV_CFG_BAR, &dev->dev_cfg_addr,
71 0, bar_size, ®_accattr, &dev->dev_cfg_handle);
74 oce_log(dev, CE_WARN, MOD_CONFIG,
81 ret = ddi_dev_regsize(dev->dip, OCE_PCI_CSR_BAR, &bar_size);
84 oce_log(dev, CE_WARN, MOD_CONFIG,
90 ret = ddi_regs_map_setup(dev->dip, OCE_PCI_CSR_BAR, &dev->csr_addr,
91 0, bar_size, ®_accattr, &dev->csr_handle);
93 oce_log(dev, CE_WARN, MOD_CONFIG,
96 ddi_regs_map_free(&dev->dev_cfg_handle);
101 ret = ddi_dev_regsize(dev->dip, OCE_PCI_DB_BAR, &bar_size);
103 oce_log(dev, CE_WARN, MOD_CONFIG,
106 ddi_regs_map_free(&dev->csr_handle);
107 ddi_regs_map_free(&dev->dev_cfg_handle);
111 ret = ddi_regs_map_setup(dev->dip, OCE_PCI_DB_BAR, &dev->db_addr,
112 0, 0, ®_accattr, &dev->db_handle);
114 oce_log(dev, CE_WARN, MOD_CONFIG,
116 ddi_regs_map_free(&dev->csr_handle);
117 ddi_regs_map_free(&dev->dev_cfg_handle);
123 oce_unmap_regs(struct oce_dev *dev)
126 ASSERT(NULL != dev);
127 ASSERT(NULL != dev->dip);
129 ddi_regs_map_free(&dev->db_handle);
130 ddi_regs_map_free(&dev->csr_handle);
131 ddi_regs_map_free(&dev->dev_cfg_handle);
142 * dev - handle to device private data structure
146 oce_pci_init(struct oce_dev *dev)
150 ret = oce_map_regs(dev);
155 dev->fn = OCE_PCI_FUNC(dev);
156 if (oce_fm_check_acc_handle(dev, dev->dev_cfg_handle) != DDI_FM_OK) {
157 ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
161 oce_pci_fini(dev);
172 * dev - handle to device private data
175 oce_pci_fini(struct oce_dev *dev)
177 oce_unmap_regs(dev);
184 * dev - handle to device private data
187 oce_get_bdf(struct oce_dev *dev)
194 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dev->dip,
199 oce_log(dev, CE_WARN, MOD_CONFIG,
204 dev->pci_bus = PCI_REG_BUS_G(pci_rp->pci_phys_hi);
205 dev->pci_device = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
206 dev->pci_function = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
208 oce_log(dev, CE_NOTE, MOD_CONFIG,
210 length, dev->pci_bus, dev->pci_device, dev->pci_function);
218 oce_identify_hw(struct oce_dev *dev)
222 dev->vendor_id = pci_config_get16(dev->pci_cfg_handle,
224 dev->device_id = pci_config_get16(dev->pci_cfg_handle,
226 dev->subsys_id = pci_config_get16(dev->pci_cfg_handle,
228 dev->subvendor_id = pci_config_get16(dev->pci_cfg_handle,
231 switch (dev->device_id) {
234 dev->chip_rev = OC_CNA_GEN2;
237 dev->chip_rev = OC_CNA_GEN3;
240 dev->chip_rev = 0;
251 * dev - software handle to the device
255 oce_is_reset_pci(struct oce_dev *dev)
259 ASSERT(dev != NULL);
260 ASSERT(dev->dip != NULL);
263 post_status.dw0 = OCE_CSR_READ32(dev, MPU_EP_SEMAPHORE);
274 * dev - software handle to the device
278 oce_pci_soft_reset(struct oce_dev *dev)
286 ASSERT(dev != NULL);
289 soft_rst.dw0 = OCE_CFG_READ32(dev, PCICFG_SOFT_RESET);
291 OCE_CFG_WRITE32(dev, PCICFG_SOFT_RESET, soft_rst.dw0);
301 soft_rst.dw0 = OCE_CFG_READ32(dev, PCICFG_SOFT_RESET);
307 oce_log(dev, CE_WARN, MOD_CONFIG,
314 return (oce_POST(dev));
319 * dev - software handle to the device
323 oce_POST(struct oce_dev *dev)
330 post_status.dw0 = OCE_CSR_READ32(dev, MPU_EP_SEMAPHORE);
331 if (oce_fm_check_acc_handle(dev, dev->csr_handle) != DDI_FM_OK) {
332 ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
338 OCE_CSR_WRITE32(dev, MPU_EP_SEMAPHORE, post_status.dw0);
339 if (oce_fm_check_acc_handle(dev, dev->csr_handle) !=
341 ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
354 post_status.dw0 = OCE_CSR_READ32(dev, MPU_EP_SEMAPHORE);
355 if (oce_fm_check_acc_handle(dev, dev->csr_handle) !=
357 ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
361 oce_log(dev, CE_WARN, MOD_CONFIG,
393 oce_create_nw_interface(struct oce_dev *dev)
399 if (dev->rss_enable) {
405 ret = oce_if_create(dev, capab_flags, capab_en_flags,
406 0, &dev->mac_addr[0], (uint32_t *)&dev->if_id);
408 oce_log(dev, CE_WARN, MOD_CONFIG,
412 atomic_inc_32(&dev->nifs);
414 dev->if_cap_flags = capab_en_flags;
417 ret = oce_config_vlan(dev, (uint8_t)dev->if_id, NULL, 0,
420 oce_log(dev, CE_WARN, MOD_CONFIG,
422 oce_delete_nw_interface(dev);
428 ret = oce_set_flow_control(dev, dev->flow_control);
430 oce_log(dev, CE_NOTE, MOD_CONFIG,
433 ret = oce_set_promiscuous(dev, dev->promisc);
436 oce_log(dev, CE_NOTE, MOD_CONFIG,
444 oce_delete_nw_interface(struct oce_dev *dev) {
447 if (dev->nifs > 0) {
448 (void) oce_if_del(dev, dev->if_id);
449 atomic_dec_32(&dev->nifs);
454 oce_create_itbl(struct oce_dev *dev, char *itbl)
457 struct oce_rq **rss_queuep = &dev->rq[1];
458 int nrss = dev->nrqs - 1;
466 oce_setup_adapter(struct oce_dev *dev)
473 oce_chip_di(dev);
475 ret = oce_create_nw_interface(dev);
479 ret = oce_create_queues(dev);
481 oce_delete_nw_interface(dev);
484 if (dev->rss_enable) {
485 (void) oce_create_itbl(dev, itbl);
487 ret = oce_config_rss(dev, dev->if_id, hkey, itbl, OCE_ITBL_SIZE,
490 oce_log(dev, CE_NOTE, MOD_CONFIG, "%s",
492 oce_delete_queues(dev);
493 oce_delete_nw_interface(dev);
497 ret = oce_setup_handlers(dev);
499 oce_log(dev, CE_NOTE, MOD_CONFIG, "%s",
501 oce_delete_queues(dev);
502 oce_delete_nw_interface(dev);
509 oce_unsetup_adapter(struct oce_dev *dev)
511 oce_remove_handler(dev);
512 if (dev->rss_enable) {
517 ret = oce_config_rss(dev, dev->if_id, hkey, itbl, OCE_ITBL_SIZE,
521 oce_log(dev, CE_NOTE, MOD_CONFIG, "%s",
525 oce_delete_queues(dev);
526 oce_delete_nw_interface(dev);
530 oce_hw_init(struct oce_dev *dev)
535 ret = oce_POST(dev);
537 oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
543 dev->bmbx = oce_alloc_dma_buffer(dev,
545 if (dev->bmbx == NULL) {
546 oce_log(dev, CE_WARN, MOD_CONFIG,
552 ret = oce_reset_fun(dev);
554 oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
560 ret = oce_mbox_init(dev);
562 oce_log(dev, CE_WARN, MOD_CONFIG,
568 ret = oce_get_fw_version(dev);
570 oce_log(dev, CE_WARN, MOD_CONFIG,
576 ret = oce_get_fw_config(dev);
578 oce_log(dev, CE_WARN, MOD_CONFIG,
584 ret = oce_read_mac_addr(dev, 0, 1,
587 oce_log(dev, CE_WARN, MOD_CONFIG,
591 bcopy(&mac_addr.mac_addr[0], &dev->mac_addr[0], ETHERADDRL);
594 oce_hw_fini(dev);
598 oce_hw_fini(struct oce_dev *dev)
600 if (dev->bmbx != NULL) {
601 oce_free_dma_buffer(dev, dev->bmbx);
602 dev->bmbx = NULL;