56 #define	FLAG_RUNNING		(1UL << 0)
57 #define	FLAG_SUSPENDED		(1UL << 1)
139 #define	COMMAND_STOP_RX		(1UL << 0)	/* Stop Receiver */
140 #define	COMMAND_START_RX	(1UL << 1)	/* Start Receiver */
141 #define	COMMAND_TXQUEUED	(1UL << 2)	/* Queue TX Descriptor */
142 #define	COMMAND_RXQUEUED	(1UL << 3)	/* Queue RX Descriptor */
143 #define	COMMAND_NEXTFRAME	(1UL << 4)	/* Release RX Frame */
144 #define	COMMAND_STOP_TDMA	(1UL << 5)	/* Stop TX DMA */
145 #define	COMMAND_STOP_RDMA	(1UL << 6)	/* Stop RX DMA */
146 #define	COMMAND_TXUGO		(1UL << 7)	/* Restart Transmission */
148 #define	INTSTAT_RCC	(1UL << 0)	/* Receive Copy Complete */
149 #define	INTSTAT_HCC	(1UL << 1)	/* Header Copy Complete */
150 #define	INTSTAT_RQE	(1UL << 2)	/* Receive Queue Empty */
151 #define	INTSTAT_OVW	(1UL << 3)	/* Receive Overflow */
152 #define	INTSTAT_RXE	(1UL << 4)	/* Receive Error */
153 #define	INTSTAT_TXC	(1UL << 5)	/* Transmit Complete */
154 #define	INTSTAT_TCC	(1UL << 6)	/* Transmit Chain Complete */
155 #define	INTSTAT_TQE	(1UL << 7)	/* Transmit Queue Empty */
156 #define	INTSTAT_TXU	(1UL << 8)	/* Transmit Underrun */
157 #define	INTSTAT_CNT	(1UL << 9)	/* Counter Overflow */
158 #define	INTSTAT_PREI	(1UL << 10)	/* Preemptive Interrupt */
159 #define	INTSTAT_RCT	(1UL << 11)	/* Receive Copy Threshold */
160 #define	INTSTAT_FATAL	(1UL << 12)	/* Fatal Error */
161 #define	INTSTAT_PME	(1UL << 14)	/* Power Management Event */
162 #define	INTSTAT_GP2	(1UL << 15)	/* GPIO Event */
163 #define	INTSTAT_ACTV	(1UL << 16)	/* Interrupt Active */
164 #define	INTSTAT_RXIDLE	(1UL << 17)	/* Receive Idle */
165 #define	INTSTAT_TXIDLE	(1UL << 18)	/* Transmit Idle */
166 #define	INTSTAT_RCIP	(1UL << 19)	/* Receive Copy in Progress */
167 #define	INTSTAT_TCIP	(1UL << 20)	/* Transmit Copy in Progress */
168 #define	INTSTAT_RBE	(1UL << 21)	/* Receive Buffers Empty */
169 #define	INTSTAT_RCTS	(1UL << 22)	/* Receive Copy Threshold Status */
170 #define	INTSTAT_RSV	(1UL << 23)	/* Receive Status Valid */
171 #define	INTSTAT_DPE	(1UL << 24)	/* PCI Data Parity Error */
172 #define	INTSTAT_APE	(1UL << 25)	/* PCI Address Parity Error */
173 #define	INTSTAT_PMA	(1UL << 26)	/* PCI Master Abort */
174 #define	INTSTAT_PTA	(1UL << 27)	/* PCI Target Abort */
176 #define	INTMASK_RCC	(1UL << 0)	/* Receive Copy Complete */
177 #define	INTMASK_HCC	(1UL << 1)	/* Header Copy Complete */
178 #define	INTMASK_RQE	(1UL << 2)	/* Receive Queue Empty */
179 #define	INTMASK_OVW	(1UL << 3)	/* Receive Overflow */
180 #define	INTMASK_RXE	(1UL << 4)	/* Receive Error */
181 #define	INTMASK_TXC	(1UL << 5)	/* Transmit Complete */
182 #define	INTMASK_TCC	(1UL << 6)	/* Transmit Chain Complete */
183 #define	INTMASK_TQE	(1UL << 7)	/* Transmit Queue Empty */
184 #define	INTMASK_TXU	(1UL << 8)	/* Transmit Underrun */
185 #define	INTMASK_CNT	(1UL << 9)	/* Counter Overflow */
186 #define	INTMASK_PREI	(1UL << 10)	/* Preemptive Interrupt */
187 #define	INTMASK_RCT	(1UL << 11)	/* Receive Copy Threshold */
188 #define	INTMASK_FATAL	(1UL << 12)	/* Fatal Error */
189 #define	INTMASK_PME	(1UL << 14)	/* Power Management Event */
190 #define	INTMASK_GP2	(1UL << 15)	/* GPIO Event */
192 #define	GENCTL_RESET	(1UL << 0)	/* Soft Reset */
193 #define	GENCTL_INT	(1UL << 1)	/* Interrupt Enable */
194 #define	GENCTL_SWINT	(1UL << 2)	/* Software Interrupt */
195 #define	GENCTL_PWRDWN	(1UL << 3)	/* Power Down */
196 #define	GENCTL_ONECOPY	(1UL << 4)	/* One Copy per Receive Frame */
197 #define	GENCTL_BE	(1UL << 5)	/* Big Endian */
198 #define	GENCTL_RDP	(1UL << 6)	/* Receive DMA Priority */
199 #define	GENCTL_TDP	(1UL << 7)	/* Transmit DMA Priority */
200 #define	GENCTL_RFT_32	(0UL << 8)	/* Receive FIFO Threshold (1/4) */
201 #define	GENCTL_RFT_64	(1UL << 8)	/* Receive FIFO Threshold (1/2) */
202 #define	GENCTL_RFT_96	(2UL << 8)	/* Receive FIFO Threshold (3/4) */
203 #define	GENCTL_RFT_128	(3UL << 8)	/* Receive FIFO Threshold (FULL) */
204 #define	GENCTL_MRM	(1UL << 10)	/* Memory Read Multiple */
205 #define	GENCTL_MRL	(1UL << 11)	/* Memory Read Line */
206 #define	GENCTL_SOFT0	(1UL << 12)	/* Software Bit 0 */
207 #define	GENCTL_SOFT1	(1UL << 13)	/* Software Bit 1 */
208 #define	GENCTL_RSTPHY	(1UL << 14)	/* PHY Reset */
209 #define	GENCTL_SCLK	(1UL << 16)	/* System Clock */
210 #define	GENCTL_RD	(1UL << 17)	/* Reset Disable */
211 #define	GENCTL_MPE	(1UL << 18)	/* Magic Packet Enable */
212 #define	GENCTL_PME	(1UL << 19)	/* PME Interrupt Enable */
213 #define	GENCTL_PS_00	(0UL << 20)	/* Power State "00" */
214 #define	GENCTL_PS_01	(1UL << 20)	/* Power State "01" */
215 #define	GENCTL_PS_10	(2UL << 20)	/* Power State "10" */
216 #define	GENCTL_PS_11	(3UL << 20)	/* Power State "11" */
217 #define	GENCTL_OPLE	(1UL << 22)	/* On Power Loss Enable */
219 #define	NVCTL_EMM	(1UL << 0)	/* Enable Memory Map */
220 #define	NVCTL_CRS	(1UL << 1)	/* Clock Run Supported */
221 #define	NVCTL_GPOE1	(1UL << 2)	/* General Purpose Output Enable 1 */
222 #define	NVCTL_GPOE2	(1UL << 3)	/* General Purpose Output Enable 2 */
223 #define	NVCTL_GPIO1	(1UL << 4)	/* General Purpose I/O 1 */
224 #define	NVCTL_GPIO2	(1UL << 5)	/* General Purpose I/O 2 */
225 #define	NVCTL_CB_MODE	(1UL << 6)	/* CardBus (UNUSED) */
228 #define	EECTL_ENABLE	(1UL << 0)	/* EEPROM Enable */
229 #define	EECTL_EECS	(1UL << 1)	/* EEPROM Chip Select */
230 #define	EECTL_EESK	(1UL << 2)	/* EEPROM Clock */
231 #define	EECTL_EEDI	(1UL << 3)	/* EEPROM Data Input */
232 #define	EECTL_EEDO	(1UL << 4)	/* EEPROM Data Output */
233 #define	EECTL_EERDY	(1UL << 5)	/* EEPROM Ready */
234 #define	EECTL_SIZE	(1UL << 6)	/* EEPROM Size */
236 #define	TEST_CLOCK	(1UL << 3)	/* Clock Test */
238 #define	MMCTL_READ	(1UL << 0)	/* MII Read */
239 #define	MMCTL_WRITE	(1UL << 1)	/* MII Write */
240 #define	MMCTL_RESPONDER	(1UL << 3)	/* MII Responder */
244 #define	MMCFG_SME	(1UL << 0)	/* Serial Mode Enable */
245 #define	MMCFG_EN694	(1UL << 1)	/* EN694 Pin */
246 #define	MMCFG_694LNK	(1UL << 2)	/* 694LNK Pin */
247 #define	MMCFG_PHY	(1UL << 3)	/* PHY Present */
248 #define	MMCFG_SMI	(1UL << 4)	/* Enable Serial Management */
249 #define	MMCFG_ALTCS	(1UL << 5)	/* Alternate Clock Source */
250 #define	MMCFG_ALTDATA	(1UL << 6)	/* Alternate Data */
251 #define	MMCFG_STXC	(1UL << 14)	/* Select TX Clock */
252 #define	MMCFG_SNTXC	(1UL << 15)	/* Set No TX Clock */
254 #define	RXCON_SEP	(1UL << 0)	/* Save Errored Packets */
255 #define	RXCON_RRF	(1UL << 1)	/* Receive Runt Frames */
256 #define	RXCON_RBF	(1UL << 2)	/* Receive Broadcast Frames */
257 #define	RXCON_RMF	(1UL << 3)	/* Receive Multicast Frames */
258 #define	RXCON_RIIA	(1UL << 4)	/* Receive Inverse Addresses */
259 #define	RXCON_PROMISC	(1UL << 5)	/* Promiscuous Mode */
260 #define	RXCON_MONITOR	(1UL << 6)	/* Monitor Mode */
261 #define	RXCON_ERE	(1UL << 7)	/* Early Receive Enable */
262 #define	RXCON_EB_INT	(0UL << 8)	/* External Buffer (Inernal) */
263 #define	RXCON_EB_16K	(1UL << 8)	/* External Buffer (16K) */
264 #define	RXCON_EB_32K	(2UL << 8)	/* External Buffer (32K) */
265 #define	RXCON_EB_128K	(3UL << 8)	/* External Buffer (128K) */
267 #define	RXSTAT_PRI	(1UL << 0)	/* Packet Received Intact */
268 #define	RXSTAT_FAE	(1UL << 1)	/* Frame Alignment Error */
269 #define	RXSTAT_CRC	(1UL << 2)	/* CRC Error */
270 #define	RXSTAT_MP	(1UL << 3)	/* Missed Packet */
271 #define	RXSTAT_MAR	(1UL << 4)	/* Multicast Address Recognized */
272 #define	RXSTAT_BAR	(1UL << 5)	/* Broadcast Address Recognized */
273 #define	RXSTAT_RD	(1UL << 6)	/* Receiver Disabled */
274 #define	RXSTAT_NSV	(1UL << 12)	/* Network Status Valid */
275 #define	RXSTAT_FLE	(1UL << 13)	/* Fragment List Error */
276 #define	RXSTAT_HC	(1UL << 14)	/* Header Copied */
277 #define	RXSTAT_OWNER	(1UL << 15)	/* Descriptor Ownership Bit */
279 #define	RXCTL_FRAGLIST	(1UL << 0)	/* Fragment List */
280 #define	RXCTL_LFFORM	(1UL << 1)	/* Fragment List Format */
281 #define	RXCTL_HEADER	(1UL << 2)	/* Header Copy */
283 #define	TXCON_ETE	(1UL << 0)	/* Early Transmit Enable */
284 #define	TXCON_LB_0	(0UL << 1)	/* Normal Operation */
285 #define	TXCON_LB_1	(1UL << 1)	/* Internal Loopback */
286 #define	TXCON_LB_2	(2UL << 1)	/* External Loopback */
287 #define	TXCON_LB_3	(3UL << 1)	/* Full Duplex Mode */
290 #define	TXSTAT_PTX	(1UL << 0)	/* Packet Transmitted */
291 #define	TXSTAT_ND	(1UL << 1)	/* Non-deferred Transmission */
292 #define	TXSTAT_COLL	(1UL << 2)	/* Transmitted w/Collisions */
293 #define	TXSTAT_CSL	(1UL << 3)	/* Carrier Sense Lost */
294 #define	TXSTAT_UFLO	(1UL << 4)	/* TX Underrun */
295 #define	TXSTAT_CDH	(1UL << 5)	/* Collision Detect Heartbeat */
296 #define	TXSTAT_OWC	(1UL << 6)	/* Out of Window Collision */
297 #define	TXSTAT_DEFER	(1UL << 7)	/* IGP Deferring */
300 #define	TXSTAT_EXCOLL	(1UL << 12)	/* Excessive Collisions */
301 #define	TXSTAT_OWNER	(1UL << 15)	/* Descriptor Ownership Bit */
303 #define	TXCTL_FRAGLIST	(1UL << 0)	/* Fragment List */
304 #define	TXCTL_LFFORM	(1UL << 1)	/* Fragment List Format */
305 #define	TXCTL_IAF	(1UL << 2)	/* Interrupt After Frame */
306 #define	TXCTL_NOCRC	(1UL << 3)	/* Disable CRC Generation */
307 #define	TXCTL_LASTDESCR	(1UL << 4)	/* Last Transmit Descriptor */

Indexes created Tue Jul 24 14:28:13 CEST 2018