Lines Matching defs:hw
406 struct e1000_hw *hw;
439 hw = &Adapter->shared;
441 hw->back = osdep;
499 (void) e1000_disable_ulp_lpt_lp(hw, TRUE);
606 struct e1000_hw *hw = &Adapter->shared;
616 mac->m_src_addr = hw->mac.addr;
633 struct e1000_hw *hw = &Adapter->shared;
637 hw->vendor_id =
639 hw->device_id =
641 hw->revision_id =
643 hw->subsystem_device_id =
645 hw->subsystem_vendor_id =
648 if (e1000_set_mac_type(hw) != E1000_SUCCESS) {
661 struct e1000_hw *hw = &Adapter->shared;
678 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr,
686 switch (hw->mac.type) {
705 (caddr_t *)&hw->flash_address, 0,
723 hw->flash_address = hw->hw_addr;
729 switch (hw->mac.type) {
765 (caddr_t *)&hw->io_base, 0, mem_size,
774 hw->io_base = 0;
783 if (osdep->ich_flash_handle != NULL && hw->mac.type != e1000_pch_spt)
791 struct e1000_hw *hw;
793 hw = &Adapter->shared;
796 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
803 if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
809 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word);
811 hw->mac.autoneg_failed = B_TRUE;
814 hw->phy.autoneg_wait_to_complete = B_FALSE;
817 hw->mac.adaptive_ifs = B_TRUE;
820 if ((hw->mac.type == e1000_82547) ||
821 (hw->mac.type == e1000_82541) ||
822 (hw->mac.type == e1000_82547_rev_2) ||
823 (hw->mac.type == e1000_82541_rev_2))
824 e1000_init_script_state_82541(hw, B_TRUE);
827 e1000_set_ttl_workaround_state_82541(hw, B_TRUE);
839 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL;
840 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
859 if (hw->phy.media_type == e1000_media_type_copper) {
860 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
861 hw->phy.disable_polarity_correction = B_FALSE;
862 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */
1366 struct e1000_hw *hw;
1370 hw = &Adapter->shared;
1377 result = e1000_reset_hw(hw);
1386 result = e1000_validate_nvm_checksum(hw);
1393 result = e1000_validate_nvm_checksum(hw);
1416 result = e1000_read_mac_addr(hw);
1427 if (!is_valid_mac_addr(hw->mac.addr)) {
1434 e1000_set_laa_state_82571(hw, B_TRUE);
1442 if (hw->mac.type < e1000_82547) {
1450 } else if ((hw->mac.type == e1000_82571) ||
1451 (hw->mac.type == e1000_82572) ||
1452 (hw->mac.type == e1000_80003es2lan)) {
1460 } else if (hw->mac.type == e1000_82573) {
1462 } else if (hw->mac.type == e1000_82574) {
1464 pba = E1000_READ_REG(hw, E1000_PBA);
1465 } else if (hw->mac.type == e1000_ich8lan) {
1467 } else if (hw->mac.type == e1000_ich9lan) {
1469 } else if (hw->mac.type == e1000_ich10lan) {
1471 } else if (hw->mac.type == e1000_pchlan) {
1473 } else if (hw->mac.type == e1000_pch2lan) {
1475 } else if (hw->mac.type == e1000_pch_lpt) {
1477 } else if (hw->mac.type == e1000_pch_spt) {
1488 E1000_WRITE_REG(hw, E1000_PBA, pba);
1505 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 ||
1506 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ?
1510 hw->fc.high_water = high_water & 0xFFF8;
1511 hw->fc.low_water = hw->fc.high_water - 8;
1513 if (hw->mac.type == e1000_80003es2lan)
1514 hw->fc.pause_time = 0xFFFF;
1516 hw->fc.pause_time = E1000_FC_PAUSE_TIME;
1517 hw->fc.send_xon = B_TRUE;
1523 result = e1000_reset_hw(hw);
1532 if (hw->mac.type >= e1000_82544)
1533 E1000_WRITE_REG(hw, E1000_WUC, 0);
1538 if (hw->mac.type == e1000_82546)
1539 e1000_pci_clear_mwi(hw);
1541 e1000_pci_set_mwi(hw);
1547 result = e1000_init_hw(hw);
1551 e1000g_log(Adapter, CE_WARN, "Initialize hw failed");
1560 (void) e1000_cleanup_led(hw);
1563 phy_spd_state(hw, B_FALSE);
1566 e1000g_get_driver_control(hw);
1577 e1000_update_mc_addr_list(hw,
1584 e1000_reset_adaptive(hw);
1587 if (hw->mac.type >= e1000_82540) {
1588 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate);
1593 if (hw->mac.autoneg)
1599 if (hw->phy.autoneg_wait_to_complete) {
1692 struct e1000_hw *hw = &Adapter->shared;
1701 switch (hw->phy.media_type) {
1703 if (hw->mac.get_link_status) {
1708 if (hw->mac.type == e1000_pch_spt)
1710 (void) e1000_check_for_link(hw);
1711 if ((E1000_READ_REG(hw, E1000_STATUS) &
1715 link_up = !hw->mac.get_link_status;
1722 (void) e1000_check_for_link(hw);
1723 link_up = (E1000_READ_REG(hw, E1000_STATUS) &
1727 (void) e1000_check_for_link(hw);
1728 link_up = hw->mac.serdes_has_link;
1976 struct e1000_hw *hw = &Adapter->shared;
1981 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
1983 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11);
1986 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
2367 struct e1000_hw *hw;
2368 hw = &Adapter->shared;
2487 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
2488 E1000_WRITE_REG(hw, E1000_RCTL,
2508 struct e1000_hw *hw;
2511 hw = &Adapter->shared;
2515 Adapter->unicst_total = min(hw->mac.rar_entry_count,
2529 if (hw->mac.type == e1000_pch_lpt ||
2530 hw->mac.type == e1000_pch_spt) {
2533 locked = E1000_READ_REG(hw, E1000_FWSM) &
2548 if ((hw->mac.type == e1000_82571) &&
2549 (e1000_get_laa_state_82571(hw) == B_TRUE))
2553 if (hw->subsystem_vendor_id == 0x15ad)
2565 if ((hw->mac.type == e1000_82571) &&
2566 (e1000_get_laa_state_82571(hw) == B_TRUE))
2567 (void) e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY);
2572 (void) e1000_rar_set(hw,
2584 struct e1000_hw *hw;
2586 hw = &Adapter->shared;
2597 if ((hw->mac.type == e1000_82542) &&
2598 (hw->revision_id == E1000_REVISION_2)) {
2599 e1000_pci_clear_mwi(hw);
2600 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
2604 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0);
2605 E1000_WRITE_FLUSH(hw);
2606 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0);
2607 E1000_WRITE_FLUSH(hw);
2614 (void) e1000_rar_set(hw, (uint8_t *)mac_addr, slot);
2620 if ((hw->mac.type == e1000_82571) &&
2621 (e1000_get_laa_state_82571(hw) == B_TRUE))
2623 E1000_WRITE_REG_ARRAY(hw, E1000_RA,
2625 E1000_WRITE_FLUSH(hw);
2626 E1000_WRITE_REG_ARRAY(hw, E1000_RA,
2628 E1000_WRITE_FLUSH(hw);
2630 (void) e1000_rar_set(hw, (uint8_t *)mac_addr,
2641 if ((hw->mac.type == e1000_82542) &&
2642 (hw->revision_id == E1000_REVISION_2)) {
2643 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2645 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2646 e1000_pci_set_mwi(hw);
2661 struct e1000_hw *hw = &Adapter->shared;
2713 e1000_update_mc_addr_list(hw,
2730 struct e1000_hw *hw = &Adapter->shared;
2770 e1000_update_mc_addr_list(hw,
2906 struct e1000_hw *hw = &adapter->shared;
2921 intr_mask = E1000_READ_REG(hw, E1000_IMS);
2923 E1000_WRITE_REG(hw, E1000_IMS, intr_mask);
2924 E1000_WRITE_FLUSH(hw);
2927 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0);
2928 E1000_WRITE_FLUSH(hw);
2939 struct e1000_hw *hw = &adapter->shared;
2952 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
2953 E1000_WRITE_FLUSH(hw);
3212 struct e1000_hw *hw = &Adapter->shared;
3237 if (hw->phy.media_type != e1000_media_type_copper) {
3245 if (hw->phy.media_type != e1000_media_type_copper) {
3253 if (hw->phy.media_type != e1000_media_type_copper) {
3261 if (hw->phy.media_type != e1000_media_type_copper) {
3269 if (hw->phy.media_type != e1000_media_type_copper) {
3277 if (hw->phy.media_type != e1000_media_type_copper) {
3513 struct e1000_hw *hw = &Adapter->shared;
3530 if (hw->phy.media_type != e1000_media_type_copper) {
3542 if (hw->phy.media_type != e1000_media_type_copper) {
3553 if (hw->phy.media_type != e1000_media_type_copper) {
3564 if (hw->phy.media_type != e1000_media_type_copper) {
3573 if (hw->phy.media_type != e1000_media_type_copper) {
3582 if (hw->phy.media_type != e1000_media_type_copper)
3587 if (hw->phy.media_type != e1000_media_type_copper) {
3663 struct e1000_hw *hw = &Adapter->shared;
3714 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay);
3735 E1000_WRITE_REG(hw, E1000_TADV,
3783 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay);
3804 E1000_WRITE_REG(hw, E1000_RADV,
3825 if (hw->mac.type >= e1000_82540) {
3828 E1000_WRITE_REG(hw, E1000_ITR,
3850 if (hw->mac.type >= e1000_82540) {
3950 struct e1000_hw *hw = &Adapter->shared;
4009 hw->fc.send_xon = B_TRUE;
4012 hw->fc.requested_mode = propval;
4014 if (hw->fc.requested_mode == 4)
4015 hw->fc.requested_mode = e1000_fc_default;
4031 hw->phy.ms_type = propval;
4040 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility);
4084 switch (hw->mac.type) {
4120 switch (hw->mac.type) {
4153 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32,
4236 struct e1000_hw *hw;
4239 hw = &Adapter->shared;
4246 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex);
4259 if ((hw->mac.type == e1000_82571) ||
4260 (hw->mac.type == e1000_82572)) {
4261 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0));
4266 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc);
4282 if (hw->phy.type == e1000_phy_igp) {
4283 (void) e1000_read_phy_reg(hw,
4286 (void) e1000_write_phy_reg(hw,
4319 struct e1000_hw *hw;
4324 hw = &Adapter->shared;
4327 if (hw->phy.media_type != e1000_media_type_copper)
4411 struct e1000_hw *hw;
4415 hw = &Adapter->shared;
4476 if ((hw->mac.type == e1000_82571) &&
4477 (e1000_get_laa_state_82571(hw) == B_TRUE)) {
4478 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0);
4479 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1);
4484 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) ||
4485 (ether_addr.mac.addr[4] != hw->mac.addr[1]) ||
4486 (ether_addr.mac.addr[3] != hw->mac.addr[2]) ||
4487 (ether_addr.mac.addr[2] != hw->mac.addr[3]) ||
4488 (ether_addr.mac.addr[1] != hw->mac.addr[4]) ||
4489 (ether_addr.mac.addr[0] != hw->mac.addr[5])) {
4490 (void) e1000_rar_set(hw, hw->mac.addr, 0);
4497 (void) e1000_igp_ttl_workaround_82547(hw);
4504 if ((hw->phy.media_type == e1000_media_type_copper) &&
4507 e1000_update_adaptive(hw);
4512 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0);
4667 struct e1000_hw *hw = &Adapter->shared;
4670 if (hw->mac.type != e1000_pchlan && hw->mac.type != e1000_pch2lan)
4675 hw->mac.autoneg = B_TRUE;
4676 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
4863 struct e1000_hw *hw = &Adapter->shared;
4871 if ((hw->phy.type != e1000_phy_igp) ||
4872 !hw->mac.autoneg ||
4873 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL))
4885 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
4889 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status);
4897 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl);
4908 (void) e1000_write_phy_reg(hw,
4917 if (!e1000_phy_setup_autoneg(hw) &&
4918 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) {
4921 (void) e1000_write_phy_reg(hw,
4943 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl);
4945 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl);
4950 if (!e1000_phy_setup_autoneg(hw) &&
4951 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) {
4954 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
5214 struct e1000_hw *hw;
5219 hw = &Adapter->shared;
5224 if (!e1000g_check_loopback_support(hw)) {
5255 (hw->phy.media_type == e1000_media_type_fiber) ||
5256 (hw->phy.media_type == e1000_media_type_internal_serdes)) {
5258 switch (hw->mac.type) {
5280 (hw->phy.media_type == e1000_media_type_fiber) ||
5281 (hw->phy.media_type == e1000_media_type_internal_serdes)) {
5283 switch (hw->mac.type) {
5306 (hw->phy.media_type == e1000_media_type_fiber) ||
5307 (hw->phy.media_type == e1000_media_type_internal_serdes)) {
5309 switch (hw->mac.type) {
5356 e1000g_check_loopback_support(struct e1000_hw *hw)
5358 switch (hw->mac.type) {
5383 struct e1000_hw *hw;
5390 hw = &Adapter->shared;
5397 hw->phy.autoneg_wait_to_complete = B_TRUE;
5399 hw->phy.autoneg_wait_to_complete = B_FALSE;
5461 hw->phy.autoneg_wait_to_complete = B_TRUE;
5463 hw->phy.autoneg_wait_to_complete = B_FALSE;
5483 struct e1000_hw *hw;
5490 hw = &Adapter->shared;
5493 phy_spd_state(hw, B_FALSE);
5495 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
5499 switch (hw->mac.type) {
5507 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
5509 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5512 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5519 (void) e1000_write_phy_reg(hw, 29, 0x001F);
5520 (void) e1000_write_phy_reg(hw, 30, 0x8FFC);
5521 (void) e1000_write_phy_reg(hw, 29, 0x001A);
5522 (void) e1000_write_phy_reg(hw, 30, 0x8FF0);
5526 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
5529 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
5539 if (hw->phy.type == e1000_phy_bm) {
5541 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg);
5544 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg);
5546 (void) e1000_phy_commit(hw);
5549 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg);
5550 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16),
5553 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg);
5554 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16),
5557 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg);
5558 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16),
5561 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg);
5562 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20),
5567 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK);
5572 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5579 switch (hw->mac.type) {
5589 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
5590 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5592 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5595 if (hw->phy.media_type == e1000_media_type_copper) {
5600 status = E1000_READ_REG(hw, E1000_STATUS);
5613 if (hw->phy.media_type != e1000_media_type_copper) {
5615 txcw = E1000_READ_REG(hw, E1000_TXCW);
5617 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
5623 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410);
5627 status = E1000_READ_REG(hw, E1000_STATUS);
5629 if ((hw->phy.media_type == e1000_media_type_fiber) &&
5633 else if (hw->phy.media_type == e1000_media_type_internal_serdes)
5645 if (hw->phy.type == e1000_phy_bm)
5648 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5654 struct e1000_hw *hw;
5662 hw = &Adapter->shared;
5665 phy_spd_state(hw, B_FALSE);
5667 switch (hw->mac.type) {
5670 switch (hw->phy.media_type) {
5673 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5675 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5677 rctl = E1000_READ_REG(hw, E1000_RCTL);
5684 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
5686 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5693 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5700 (void) e1000_write_phy_reg(hw, 0x0, 0x140);
5702 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00);
5703 (void) e1000_write_phy_reg(hw, 0x12, 0xC10);
5704 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10);
5705 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76);
5706 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1);
5707 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0);
5709 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65);
5710 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C);
5711 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC);
5712 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C);
5713 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC);
5719 status = E1000_READ_REG(hw, E1000_STATUS);
5721 (hw->phy.media_type ==
5723 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5725 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5729 txcw = E1000_READ_REG(hw, E1000_TXCW);
5731 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
5737 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410);
5748 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata);
5749 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16),
5761 struct e1000_hw *hw;
5765 hw = &Adapter->shared;
5768 phy_spd_state(hw, B_FALSE);
5774 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5779 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5784 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5792 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5798 struct e1000_hw *hw;
5802 hw = &Adapter->shared;
5805 phy_spd_state(hw, B_FALSE);
5811 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5816 (void) e1000_write_phy_reg(hw, PHY_CONTROL,
5821 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5829 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5836 struct e1000_hw *hw = &Adapter->shared;
5857 hw->mac.addr[nelts] = bytes[nelts];
5871 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
5889 hw->mac.addr[nelts] = bytes[nelts];
5896 bcopy(hw->mac.addr, hw->mac.perm_addr,
6194 struct e1000_hw *hw = &Adapter->shared;
6196 if (hw->phy.media_type == e1000_media_type_copper) {
6197 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl);
6198 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status);
6199 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
6201 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP,
6203 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS,
6205 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL,
6207 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6209 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY,
6237 Adapter->param_adv_autoneg = hw->mac.autoneg;
6504 e1000g_get_driver_control(struct e1000_hw *hw)
6510 switch (hw->mac.type) {
6512 swsm = E1000_READ_REG(hw, E1000_SWSM);
6513 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
6524 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
6525 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
6539 e1000g_release_driver_control(struct e1000_hw *hw)
6545 switch (hw->mac.type) {
6547 swsm = E1000_READ_REG(hw, E1000_SWSM);
6548 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
6559 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
6560 E1000_WRITE_REG(hw, E1000_CTRL_EXT,