Lines Matching refs:hw
37 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
66 * @hw: pointer to the HW structure
70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 struct e1000_phy_info *phy = &hw->phy;
105 * @hw: pointer to the HW structure
107 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
116 * @hw: pointer to the HW structure
118 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
127 * @hw: pointer to the HW structure
129 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
137 * @hw: pointer to the HW structure
139 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
148 * @hw: pointer to the HW structure
150 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
159 * @hw: pointer to hardware structure
165 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
176 * @hw: pointer to hardware structure
182 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
193 * @hw: pointer to the HW structure
199 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
205 manc = E1000_READ_REG(hw, E1000_MANC);
213 * @hw: pointer to the HW structure
218 s32 e1000_get_phy_id(struct e1000_hw *hw)
220 struct e1000_phy_info *phy = &hw->phy;
231 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
237 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
255 * @hw: pointer to the HW structure
259 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
265 if (!hw->phy.ops.write_reg)
268 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
272 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
277 * @hw: pointer to the HW structure
284 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
286 struct e1000_phy_info *phy = &hw->phy;
304 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
312 mdic = E1000_READ_REG(hw, E1000_MDIC);
335 if (hw->mac.type == e1000_pch2lan)
343 * @hw: pointer to the HW structure
349 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
351 struct e1000_phy_info *phy = &hw->phy;
370 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
378 mdic = E1000_READ_REG(hw, E1000_MDIC);
400 if (hw->mac.type == e1000_pch2lan)
408 * @hw: pointer to the HW structure
415 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
417 struct e1000_phy_info *phy = &hw->phy;
430 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
435 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
456 * @hw: pointer to the HW structure
462 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
464 struct e1000_phy_info *phy = &hw->phy;
471 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
473 hw->phy.addr);
489 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
494 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
512 * @hw: pointer to the HW structure
523 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
543 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
548 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
567 * @hw: pointer to the HW structure
578 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
602 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
608 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
621 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
640 * @hw: pointer to the HW structure
648 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
654 if (!hw->phy.ops.acquire)
657 ret_val = hw->phy.ops.acquire(hw);
661 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
664 hw->phy.ops.release(hw);
671 * @hw: pointer to the HW structure
678 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
684 if (!hw->phy.ops.acquire)
687 ret_val = hw->phy.ops.acquire(hw);
691 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
694 hw->phy.ops.release(hw);
701 * @hw: pointer to the HW structure
708 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
714 hw->phy.addr = 1;
716 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
721 * @hw: pointer to the HW structure
730 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
738 if (!hw->phy.ops.acquire)
741 ret_val = hw->phy.ops.acquire(hw);
747 ret_val = e1000_write_phy_reg_mdic(hw,
751 ret_val = e1000_read_phy_reg_mdic(hw,
755 hw->phy.ops.release(hw);
762 * @hw: pointer to the HW structure
770 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
772 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
777 * @hw: pointer to the HW structure
784 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
786 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
791 * @hw: pointer to the HW structure
799 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
807 if (!hw->phy.ops.acquire)
810 ret_val = hw->phy.ops.acquire(hw);
816 ret_val = e1000_write_phy_reg_mdic(hw,
820 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
824 hw->phy.ops.release(hw);
831 * @hw: pointer to the HW structure
838 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
840 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
845 * @hw: pointer to the HW structure
852 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
854 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
859 * @hw: pointer to the HW structure
868 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
878 if (!hw->phy.ops.acquire)
881 ret_val = hw->phy.ops.acquire(hw);
888 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
889 E1000_WRITE_FLUSH(hw);
893 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
897 hw->phy.ops.release(hw);
904 * @hw: pointer to the HW structure
912 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
914 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
919 * @hw: pointer to the HW structure
927 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
929 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
934 * @hw: pointer to the HW structure
943 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
953 if (!hw->phy.ops.acquire)
956 ret_val = hw->phy.ops.acquire(hw);
963 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
964 E1000_WRITE_FLUSH(hw);
969 hw->phy.ops.release(hw);
976 * @hw: pointer to the HW structure
983 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
985 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
990 * @hw: pointer to the HW structure
997 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
999 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
1004 * @hw: pointer to the HW structure
1008 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1014 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1019 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1024 switch (hw->phy.ms_type) {
1039 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1044 * @hw: pointer to the HW structure
1048 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1055 if (hw->phy.type == e1000_phy_82580) {
1056 ret_val = hw->phy.ops.reset(hw);
1064 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1073 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1078 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1087 switch (hw->phy.mdix) {
1098 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1102 return e1000_set_master_slave_mode(hw);
1107 * @hw: pointer to the HW structure
1112 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1114 struct e1000_phy_info *phy = &hw->phy;
1122 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1170 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1175 ret_val = phy->ops.commit(hw);
1185 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1195 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1214 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1222 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1227 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1233 ret_val = phy->ops.commit(hw);
1240 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1248 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1259 * @hw: pointer to the HW structure
1264 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1266 struct e1000_phy_info *phy = &hw->phy;
1274 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1320 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1324 ret_val = phy->ops.commit(hw);
1335 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1340 ret_val = phy->ops.commit(hw);
1346 ret_val = e1000_set_master_slave_mode(hw);
1355 * @hw: pointer to the HW structure
1360 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1362 struct e1000_phy_info *phy = &hw->phy;
1369 ret_val = hw->phy.ops.reset(hw);
1385 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1393 if (hw->phy.ops.set_d0_lplu_state) {
1394 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1401 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1419 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1424 if (hw->mac.autoneg) {
1431 ret_val = phy->ops.read_reg(hw,
1438 ret_val = phy->ops.write_reg(hw,
1445 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1450 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1455 ret_val = e1000_set_master_slave_mode(hw);
1463 * @hw: pointer to the HW structure
1470 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1472 struct e1000_phy_info *phy = &hw->phy;
1482 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1488 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1564 switch (hw->fc.current_mode) {
1579 * hw's ability to send PAUSE frames.
1601 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1608 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1616 * @hw: pointer to the HW structure
1623 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1625 struct e1000_phy_info *phy = &hw->phy;
1643 ret_val = e1000_phy_setup_autoneg(hw);
1653 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1658 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1666 ret_val = e1000_wait_autoneg(hw);
1673 hw->mac.get_link_status = TRUE;
1680 * @hw: pointer to the HW structure
1687 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1694 if (hw->mac.autoneg) {
1698 ret_val = e1000_copper_link_autoneg(hw);
1706 ret_val = hw->phy.ops.force_speed_duplex(hw);
1716 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1723 hw->mac.ops.config_collision_dist(hw);
1724 ret_val = e1000_config_fc_after_link_up_generic(hw);
1734 * @hw: pointer to the HW structure
1740 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1742 struct e1000_phy_info *phy = &hw->phy;
1749 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1753 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1755 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1762 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1769 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1780 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1789 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1798 * @hw: pointer to the HW structure
1806 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1808 struct e1000_phy_info *phy = &hw->phy;
1820 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1826 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1834 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1838 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1840 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1845 ret_val = hw->phy.ops.commit(hw);
1852 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1860 switch (hw->phy.id) {
1870 if (hw->phy.type != e1000_phy_m88)
1881 ret_val = phy->ops.write_reg(hw,
1886 ret_val = e1000_phy_reset_dsp_generic(hw);
1893 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1899 if (hw->phy.type != e1000_phy_m88)
1902 if (hw->phy.id == I347AT4_E_PHY_ID ||
1903 hw->phy.id == M88E1340M_E_PHY_ID ||
1904 hw->phy.id == M88E1112_E_PHY_ID)
1906 if (hw->phy.id == I210_I_PHY_ID)
1908 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1909 (hw->phy.id == M88E1512_E_PHY_ID))
1911 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1920 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1927 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1932 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1939 * @hw: pointer to the HW structure
1945 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1947 struct e1000_phy_info *phy = &hw->phy;
1954 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1958 e1000_phy_force_speed_duplex_setup(hw, &data);
1960 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1965 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1972 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1983 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1992 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2003 * @hw: pointer to the HW structure
2013 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2015 struct e1000_mac_info *mac = &hw->mac;
2021 hw->fc.current_mode = e1000_fc_none;
2024 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2057 hw->mac.ops.config_collision_dist(hw);
2059 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2064 * @hw: pointer to the HW structure
2076 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2078 struct e1000_phy_info *phy = &hw->phy;
2084 if (!hw->phy.ops.read_reg)
2087 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2093 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2103 ret_val = phy->ops.read_reg(hw,
2110 ret_val = phy->ops.write_reg(hw,
2116 ret_val = phy->ops.read_reg(hw,
2123 ret_val = phy->ops.write_reg(hw,
2133 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2139 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2145 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2154 * @hw: pointer to the HW structure
2160 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2162 struct e1000_phy_info *phy = &hw->phy;
2189 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2199 * @hw: pointer to the HW structure
2205 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2207 struct e1000_phy_info *phy = &hw->phy;
2213 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2225 * @hw: pointer to the HW structure
2232 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2234 struct e1000_phy_info *phy = &hw->phy;
2243 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2259 ret_val = phy->ops.read_reg(hw, offset, &data);
2271 * @hw: pointer to the HW structure
2275 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2277 struct e1000_phy_info *phy = &hw->phy;
2293 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2305 * @hw: pointer to the HW structure
2310 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2317 if (!hw->phy.ops.read_reg)
2322 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2325 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2341 * @hw: pointer to the HW structure
2348 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2356 if (!hw->phy.ops.read_reg)
2364 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2375 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2393 * @hw: pointer to the HW structure
2406 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2408 struct e1000_phy_info *phy = &hw->phy;
2414 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2432 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2434 struct e1000_phy_info *phy = &hw->phy;
2441 switch (hw->phy.id) {
2444 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2451 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2468 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2473 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2478 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2484 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2496 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2504 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2509 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2513 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2531 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2546 * @hw: pointer to the HW structure
2555 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2557 struct e1000_phy_info *phy = &hw->phy;
2573 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2617 * @hw: pointer to the HW structure
2625 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2627 struct e1000_phy_info *phy = &hw->phy;
2639 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2648 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2655 ret_val = e1000_check_polarity_m88(hw);
2659 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2666 ret_val = hw->phy.ops.get_cable_length(hw);
2670 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2693 * @hw: pointer to the HW structure
2700 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2702 struct e1000_phy_info *phy = &hw->phy;
2709 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2720 ret_val = e1000_check_polarity_igp(hw);
2724 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2732 ret_val = phy->ops.get_cable_length(hw);
2736 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2758 * @hw: pointer to the HW structure
2762 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2764 struct e1000_phy_info *phy = &hw->phy;
2771 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2780 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2786 ret_val = e1000_check_polarity_ife(hw);
2796 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2812 * @hw: pointer to the HW structure
2817 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2824 if (!hw->phy.ops.read_reg)
2827 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2832 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2843 * @hw: pointer to the HW structure
2850 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2852 struct e1000_phy_info *phy = &hw->phy;
2859 ret_val = phy->ops.check_reset_block(hw);
2864 ret_val = phy->ops.acquire(hw);
2868 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2869 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2870 E1000_WRITE_FLUSH(hw);
2874 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2875 E1000_WRITE_FLUSH(hw);
2879 phy->ops.release(hw);
2881 return phy->ops.get_cfg_done(hw);
2886 * @hw: pointer to the HW structure
2891 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2902 * @hw: pointer to the HW structure
2906 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2912 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2914 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2916 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2918 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2920 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2922 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2924 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2926 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2928 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2930 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2932 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2934 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2936 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2938 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2940 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2942 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2944 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2946 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2948 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2950 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2952 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2954 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2956 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2958 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2960 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2962 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2966 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2968 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2972 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2974 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2976 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2978 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
3050 * @hw: pointer to the HW structure
3056 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3062 hw->phy.id = phy_type;
3065 hw->phy.addr = phy_addr;
3069 e1000_get_phy_id(hw);
3070 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3104 * @hw: pointer to the HW structure
3111 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3118 ret_val = hw->phy.ops.acquire(hw);
3124 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3129 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3138 if (hw->phy.addr == 1) {
3147 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3153 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3157 hw->phy.ops.release(hw);
3163 * @hw: pointer to the HW structure
3171 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3178 ret_val = hw->phy.ops.acquire(hw);
3184 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3189 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3198 if (hw->phy.addr == 1) {
3207 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3213 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3216 hw->phy.ops.release(hw);
3222 * @hw: pointer to the HW structure
3230 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3237 ret_val = hw->phy.ops.acquire(hw);
3243 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3248 hw->phy.addr = 1;
3252 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3259 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3262 hw->phy.ops.release(hw);
3268 * @hw: pointer to the HW structure
3275 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3282 ret_val = hw->phy.ops.acquire(hw);
3288 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3293 hw->phy.addr = 1;
3297 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3304 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3308 hw->phy.ops.release(hw);
3314 * @hw: pointer to the HW structure
3320 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3331 hw->phy.addr = 1;
3334 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3340 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3354 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3364 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3369 * @hw: pointer to the HW structure
3378 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3388 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3395 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3405 * @hw: pointer to the HW structure
3428 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3439 if ((hw->mac.type == e1000_pchlan) &&
3440 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3446 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3456 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3464 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3468 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3478 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3485 * @hw: pointer to the HW structure
3491 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3496 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3498 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3503 * @hw: pointer to the HW structure
3509 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3514 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3516 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3522 * @hw: pointer to the HW structure
3531 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3537 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3542 ret_val = hw->phy.ops.acquire(hw);
3548 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3554 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3565 ret_val = e1000_set_page_igp(hw,
3568 hw->phy.addr = phy_addr;
3578 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3582 hw->phy.ops.release(hw);
3589 * @hw: pointer to the HW structure
3597 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3599 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, false);
3604 * @hw: pointer to the HW structure
3611 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3613 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3618 * @hw: pointer to the HW structure
3625 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3627 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true);
3632 * @hw: pointer to the HW structure
3640 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3646 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3651 ret_val = hw->phy.ops.acquire(hw);
3657 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3663 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3675 if ((hw->phy.type == e1000_phy_82578) &&
3676 (hw->phy.revision >= 1) &&
3677 (hw->phy.addr == 2) &&
3681 ret_val = e1000_access_phy_debug_regs_hv(hw,
3690 ret_val = e1000_set_page_igp(hw,
3693 hw->phy.addr = phy_addr;
3703 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3708 hw->phy.ops.release(hw);
3715 * @hw: pointer to the HW structure
3722 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3724 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, false);
3729 * @hw: pointer to the HW structure
3736 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3738 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
3743 * @hw: pointer to the HW structure
3750 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3752 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true);
3771 * @hw: pointer to the HW structure
3781 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3791 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3796 hw->phy.addr = 2;
3799 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3807 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3809 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3819 * @hw: pointer to the HW structure
3828 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3835 if (hw->phy.type != e1000_phy_82578)
3839 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3844 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3858 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3864 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3870 * @hw: pointer to the HW structure
3876 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3878 struct e1000_phy_info *phy = &hw->phy;
3884 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3896 * @hw: pointer to the HW structure
3900 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3902 struct e1000_phy_info *phy = &hw->phy;
3909 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3913 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3915 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3924 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3933 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3942 * @hw: pointer to the HW structure
3949 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3951 struct e1000_phy_info *phy = &hw->phy;
3958 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3969 ret_val = e1000_check_polarity_82577(hw);
3973 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3981 ret_val = hw->phy.ops.get_cable_length(hw);
3985 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4007 * @hw: pointer to the HW structure
4012 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4014 struct e1000_phy_info *phy = &hw->phy;
4020 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4037 * @hw: pointer to the HW structure
4044 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4052 ret_val = hw->phy.ops.acquire(hw);
4056 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4059 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4062 hw->phy.ops.release(hw);
4068 * @hw: pointer to the HW structure
4076 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4084 ret_val = hw->phy.ops.acquire(hw);
4088 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4091 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4094 hw->phy.ops.release(hw);
4100 * @hw: pointer to the HW structure
4107 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4116 ready = e1000_is_mphy_ready(hw);
4121 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4124 ready = e1000_is_mphy_ready(hw);
4128 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4132 ready = e1000_is_mphy_ready(hw);
4140 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4143 ready = e1000_is_mphy_ready(hw);
4146 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4150 ready = e1000_is_mphy_ready(hw);
4153 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4161 * @hw: pointer to the HW structure
4168 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4178 ready = e1000_is_mphy_ready(hw);
4183 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4186 ready = e1000_is_mphy_ready(hw);
4190 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4194 ready = e1000_is_mphy_ready(hw);
4205 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4208 ready = e1000_is_mphy_ready(hw);
4211 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4215 ready = e1000_is_mphy_ready(hw);
4218 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4226 * @hw: pointer to the HW structure
4230 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4237 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);