Cross Reference: /illumos-gate/usr/src/uts/common/io/e1000api/e1000

Lines Matching defs:nvm
47 	struct e1000_nvm_info *nvm = &hw->nvm;
51 	nvm->ops.init_params = e1000_null_ops_generic;
52 	nvm->ops.acquire = e1000_null_ops_generic;
53 	nvm->ops.read = e1000_null_read_nvm;
54 	nvm->ops.release = e1000_null_nvm_generic;
55 	nvm->ops.reload = e1000_reload_nvm_generic;
56 	nvm->ops.update = e1000_null_ops_generic;
57 	nvm->ops.valid_led_default = e1000_null_led_default;
58 	nvm->ops.validate = e1000_null_ops_generic;
59 	nvm->ops.write = e1000_null_write_nvm;
119 	usec_delay(hw->nvm.delay_usec);
134 	usec_delay(hw->nvm.delay_usec);
149 	struct e1000_nvm_info *nvm = &hw->nvm;
156 	if (nvm->type == e1000_nvm_eeprom_microwire)
159 	if (nvm->type == e1000_nvm_eeprom_spi)
171 		usec_delay(nvm->delay_usec);
297 	struct e1000_nvm_info *nvm = &hw->nvm;
302 	if (nvm->type == e1000_nvm_eeprom_microwire) {
306 		usec_delay(nvm->delay_usec);
314 		usec_delay(nvm->delay_usec);
317 	} else if (nvm->type == e1000_nvm_eeprom_spi) {
322 		usec_delay(nvm->delay_usec);
326 		usec_delay(nvm->delay_usec);
343 	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
347 	} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
383 	struct e1000_nvm_info *nvm = &hw->nvm;
389 	if (nvm->type == e1000_nvm_eeprom_microwire) {
396 	} else if (nvm->type == e1000_nvm_eeprom_spi) {
412 						 hw->nvm.opcode_bits);
442 	struct e1000_nvm_info *nvm = &hw->nvm;
453 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
455 		DEBUGOUT("nvm parameter(s) out of bounds\n");
459 	ret_val = nvm->ops.acquire(hw);
469 	if ((nvm->address_bits == 8) && (offset >= 128))
473 	e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
474 	e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
486 	nvm->ops.release(hw);
503 	struct e1000_nvm_info *nvm = &hw->nvm;
513 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
515 		DEBUGOUT("nvm parameter(s) out of bounds\n");
519 	ret_val = nvm->ops.acquire(hw);
529 		e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
531 					nvm->address_bits);
541 	nvm->ops.release(hw);
557 	struct e1000_nvm_info *nvm = &hw->nvm;
566 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
568 		DEBUGOUT("nvm parameter(s) out of bounds\n");
605 	struct e1000_nvm_info *nvm = &hw->nvm;
614 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
616 		DEBUGOUT("nvm parameter(s) out of bounds\n");
623 		ret_val = nvm->ops.acquire(hw);
629 			nvm->ops.release(hw);
637 					 nvm->opcode_bits);
644 		if ((nvm->address_bits == 8) && (offset >= 128))
648 		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
650 					 nvm->address_bits);
659 			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
665 		nvm->ops.release(hw);
686 	struct e1000_nvm_info *nvm = &hw->nvm;
697 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
699 		DEBUGOUT("nvm parameter(s) out of bounds\n");
703 	ret_val = nvm->ops.acquire(hw);
712 				 (u16)(nvm->opcode_bits + 2));
714 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
720 					 nvm->opcode_bits);
723 					 nvm->address_bits);
748 				 (u16)(nvm->opcode_bits + 2));
750 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
753 	nvm->ops.release(hw);
789 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
795 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
840 	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
861 		ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
896 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
902 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
914 	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
1167 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1200 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1208 	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);