Lines Matching refs:ctrl
778 u32 ctrl;
784 ctrl = E1000_READ_REG(hw, E1000_CTRL);
795 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
796 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
808 ctrl = E1000_READ_REG(hw, E1000_CTRL);
809 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
810 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
818 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
826 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
845 u32 ctrl;
851 ctrl = E1000_READ_REG(hw, E1000_CTRL);
861 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
873 ctrl = E1000_READ_REG(hw, E1000_CTRL);
874 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
875 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
883 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
891 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1178 u32 ctrl;
1183 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1186 ctrl &= ~E1000_CTRL_LRST;
1202 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1291 u32 ctrl;
1295 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1318 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1321 ctrl &= (~E1000_CTRL_TFCE);
1322 ctrl |= E1000_CTRL_RFCE;
1325 ctrl &= (~E1000_CTRL_RFCE);
1326 ctrl |= E1000_CTRL_TFCE;
1329 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1336 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2000 u32 ctrl;
2006 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2007 ctrl &= ~E1000_CTRL_SWDPIN0;
2008 ctrl |= E1000_CTRL_SWDPIO0;
2009 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2029 u32 ctrl;
2035 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2036 ctrl |= E1000_CTRL_SWDPIN0;
2037 ctrl |= E1000_CTRL_SWDPIO0;
2038 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2087 u32 ctrl;
2095 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2096 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2097 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);