Lines Matching refs:ret_val
204 s32 ret_val = 0;
209 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
210 if (ret_val || (phy_reg == 0xFFFF))
214 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
215 if (ret_val || (phy_reg == 0xFFFF)) {
237 ret_val = e1000_set_mdio_slow_mode_hv(hw);
238 if (!ret_val)
239 ret_val = e1000_get_phy_id(hw);
243 if (ret_val)
320 s32 ret_val;
335 ret_val = hw->phy.ops.acquire(hw);
336 if (ret_val) {
377 ret_val = -E1000_ERR_PHY;
397 ret_val = -E1000_ERR_PHY;
405 if (!ret_val) {
418 ret_val = e1000_phy_hw_reset_generic(hw);
419 if (ret_val)
428 ret_val = hw->phy.ops.check_reset_block(hw);
429 if (ret_val)
441 return ret_val;
453 s32 ret_val;
480 ret_val = e1000_init_phy_workarounds_pchlan(hw);
481 if (ret_val)
482 return ret_val;
487 ret_val = e1000_get_phy_id(hw);
488 if (ret_val)
489 return ret_val;
499 ret_val = e1000_set_mdio_slow_mode_hv(hw);
500 if (ret_val)
501 return ret_val;
502 ret_val = e1000_get_phy_id(hw);
503 if (ret_val)
504 return ret_val;
527 ret_val = -E1000_ERR_PHY;
531 return ret_val;
543 s32 ret_val;
567 ret_val = e1000_determine_phy_address(hw);
568 if (ret_val) {
571 ret_val = e1000_determine_phy_address(hw);
572 if (ret_val) {
574 return ret_val;
582 ret_val = e1000_get_phy_id(hw);
583 if (ret_val)
584 return ret_val;
845 s32 ret_val;
849 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
850 if (ret_val)
851 return ret_val;
854 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
857 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
860 return ret_val;
910 s32 ret_val;
930 ret_val = hw->phy.ops.acquire(hw);
931 if (ret_val)
932 return ret_val;
934 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
935 if (ret_val)
944 ret_val = e1000_read_emi_reg_locked(hw, lpa,
946 if (ret_val)
950 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
951 if (ret_val)
975 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
977 if (ret_val)
981 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
986 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
987 if (ret_val)
990 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
994 return ret_val;
1012 s32 ret_val = E1000_SUCCESS;
1016 ret_val = hw->phy.ops.acquire(hw);
1017 if (ret_val)
1018 return ret_val;
1020 ret_val =
1023 if (ret_val)
1026 ret_val =
1031 if (ret_val)
1039 ret_val =
1054 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1055 if (ret_val)
1056 return ret_val;
1076 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1077 if (ret_val)
1078 return ret_val;
1084 return ret_val;
1262 s32 ret_val = E1000_SUCCESS;
1304 ret_val = hw->phy.ops.acquire(hw);
1305 if (ret_val)
1309 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1310 if (ret_val)
1324 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1326 if (ret_val)
1332 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1335 if (ret_val)
1342 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1343 if (ret_val)
1373 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1375 if (ret_val)
1382 if (ret_val)
1383 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1387 return ret_val;
1407 s32 ret_val = E1000_SUCCESS;
1433 ret_val = -E1000_ERR_PHY;
1455 ret_val = hw->phy.ops.acquire(hw);
1456 if (ret_val)
1464 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1465 if (ret_val) {
1475 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1477 if (ret_val)
1491 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1492 if (ret_val)
1498 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1499 if (ret_val)
1527 if (ret_val)
1528 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1532 return ret_val;
1546 s32 ret_val, tipg_reg = 0;
1565 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1566 if (ret_val)
1567 return ret_val;
1570 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1571 if (ret_val)
1572 return ret_val;
1604 ret_val = hw->phy.ops.acquire(hw);
1605 if (ret_val)
1606 return ret_val;
1612 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1641 if (ret_val)
1642 return ret_val;
1649 ret_val = hw->phy.ops.acquire(hw);
1650 if (ret_val)
1651 return ret_val;
1653 ret_val = hw->phy.ops.read_reg_locked(hw,
1656 if (ret_val) {
1658 return ret_val;
1665 ret_val =
1670 if (ret_val)
1671 return ret_val;
1673 ret_val = hw->phy.ops.acquire(hw);
1674 if (ret_val)
1675 return ret_val;
1677 ret_val = hw->phy.ops.write_reg_locked(hw,
1681 if (ret_val)
1682 return ret_val;
1708 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1709 if (ret_val)
1710 return ret_val;
1718 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1719 if (ret_val)
1720 return ret_val;
1747 ret_val = e1000_k1_workaround_lv(hw);
1748 if (ret_val)
1749 return ret_val;
1753 ret_val = e1000_link_stall_workaround_hv(hw);
1754 if (ret_val)
1755 return ret_val;
1783 ret_val = e1000_set_eee_pchlan(hw);
1784 if (ret_val)
1785 return ret_val;
1805 ret_val = e1000_config_fc_after_link_up_generic(hw);
1806 if (ret_val)
1809 return ret_val;
1881 s32 ret_val = E1000_SUCCESS;
1898 ret_val = -E1000_ERR_CONFIG;
1921 ret_val = -E1000_ERR_CONFIG;
1926 if (ret_val)
1929 return ret_val;
2042 s32 ret_val;
2044 ret_val = e1000_acquire_swflag_ich8lan(hw);
2045 if (ret_val)
2120 s32 ret_val;
2122 ret_val = e1000_acquire_swflag_ich8lan(hw);
2124 if (ret_val)
2163 s32 ret_val;
2169 ret_val = hw->phy.ops.acquire(hw);
2170 if (ret_val)
2173 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2174 if (ret_val)
2233 s32 ret_val;
2237 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2238 if (ret_val)
2239 return ret_val;
2272 s32 ret_val = E1000_SUCCESS;
2286 return ret_val;
2301 return ret_val;
2304 ret_val = hw->phy.ops.acquire(hw);
2305 if (ret_val)
2306 return ret_val;
2337 ret_val = e1000_write_smbus_addr(hw);
2338 if (ret_val)
2342 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2344 if (ret_val)
2354 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2356 if (ret_val)
2359 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2361 if (ret_val)
2373 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2375 if (ret_val)
2381 return ret_val;
2396 s32 ret_val = E1000_SUCCESS;
2406 ret_val = hw->phy.ops.acquire(hw);
2407 if (ret_val)
2408 return ret_val;
2413 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2415 if (ret_val)
2429 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2431 if (ret_val)
2445 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2447 if (ret_val)
2452 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2454 if (ret_val)
2458 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2463 return ret_val;
2478 s32 ret_val;
2486 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2488 if (ret_val)
2489 return ret_val;
2496 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2498 if (ret_val)
2499 return ret_val;
2531 s32 ret_val = 0;
2538 return ret_val;
2540 ret_val = hw->phy.ops.acquire(hw);
2541 if (ret_val)
2542 return ret_val;
2556 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2557 if (ret_val)
2583 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2588 return ret_val;
2598 s32 ret_val;
2603 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2604 if (ret_val)
2605 return ret_val;
2609 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2611 return ret_val;
2620 s32 ret_val = E1000_SUCCESS;
2630 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2631 if (ret_val)
2632 return ret_val;
2639 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2640 if (ret_val)
2641 return ret_val;
2644 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2646 if (ret_val)
2647 return ret_val;
2656 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2662 ret_val = hw->phy.ops.acquire(hw);
2663 if (ret_val)
2664 return ret_val;
2667 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2669 if (ret_val)
2670 return ret_val;
2675 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2676 if (ret_val)
2677 return ret_val;
2680 ret_val = hw->phy.ops.acquire(hw);
2681 if (ret_val)
2682 return ret_val;
2683 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2684 if (ret_val)
2686 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2688 if (ret_val)
2692 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2696 return ret_val;
2707 s32 ret_val;
2711 ret_val = hw->phy.ops.acquire(hw);
2712 if (ret_val)
2714 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2715 if (ret_val)
2766 s32 ret_val = E1000_SUCCESS;
2778 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2780 if (ret_val)
2781 return ret_val;
2819 ret_val = e1000_read_kmrn_reg_generic(hw,
2822 if (ret_val)
2823 return ret_val;
2824 ret_val = e1000_write_kmrn_reg_generic(hw,
2827 if (ret_val)
2828 return ret_val;
2829 ret_val = e1000_read_kmrn_reg_generic(hw,
2832 if (ret_val)
2833 return ret_val;
2836 ret_val = e1000_write_kmrn_reg_generic(hw,
2839 if (ret_val)
2840 return ret_val;
2846 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2847 if (ret_val)
2848 return ret_val;
2851 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2852 if (ret_val)
2853 return ret_val;
2857 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2858 if (ret_val)
2859 return ret_val;
2860 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2861 if (ret_val)
2862 return ret_val;
2864 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2866 if (ret_val)
2867 return ret_val;
2878 ret_val = e1000_read_kmrn_reg_generic(hw,
2881 if (ret_val)
2882 return ret_val;
2883 ret_val = e1000_write_kmrn_reg_generic(hw,
2886 if (ret_val)
2887 return ret_val;
2888 ret_val = e1000_read_kmrn_reg_generic(hw,
2891 if (ret_val)
2892 return ret_val;
2895 ret_val = e1000_write_kmrn_reg_generic(hw,
2898 if (ret_val)
2899 return ret_val;
2904 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2905 if (ret_val)
2906 return ret_val;
2909 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2910 if (ret_val)
2911 return ret_val;
2915 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2916 if (ret_val)
2917 return ret_val;
2918 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2919 if (ret_val)
2920 return ret_val;
2922 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2924 if (ret_val)
2925 return ret_val;
2939 s32 ret_val = E1000_SUCCESS;
2947 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2948 if (ret_val)
2949 return ret_val;
2951 ret_val = hw->phy.ops.acquire(hw);
2952 if (ret_val)
2953 return ret_val;
2955 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2956 if (ret_val)
2959 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2963 return ret_val;
2975 s32 ret_val = E1000_SUCCESS;
2984 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2985 if (ret_val)
2986 return ret_val;
2995 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2997 if (ret_val)
2998 return ret_val;
3000 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
3002 if (ret_val)
3003 return ret_val;
3013 return ret_val;
3082 s32 ret_val = E1000_SUCCESS;
3096 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3097 if (ret_val)
3098 return ret_val;
3101 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3102 if (ret_val)
3103 return ret_val;
3117 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3118 if (ret_val)
3119 return ret_val;
3122 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
3133 ret_val = hw->phy.ops.acquire(hw);
3134 if (ret_val)
3135 return ret_val;
3136 ret_val = e1000_write_emi_reg_locked(hw,
3142 return ret_val;
3155 s32 ret_val = E1000_SUCCESS;
3164 ret_val = e1000_phy_hw_reset_generic(hw);
3165 if (ret_val)
3166 return ret_val;
3184 s32 ret_val;
3188 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3189 if (ret_val)
3190 return ret_val;
3220 s32 ret_val = E1000_SUCCESS;
3244 ret_val = phy->ops.read_reg(hw,
3247 if (ret_val)
3248 return ret_val;
3250 ret_val = phy->ops.write_reg(hw,
3253 if (ret_val)
3254 return ret_val;
3268 ret_val = phy->ops.read_reg(hw,
3271 if (ret_val)
3272 return ret_val;
3275 ret_val = phy->ops.write_reg(hw,
3278 if (ret_val)
3279 return ret_val;
3281 ret_val = phy->ops.read_reg(hw,
3284 if (ret_val)
3285 return ret_val;
3288 ret_val = phy->ops.write_reg(hw,
3291 if (ret_val)
3292 return ret_val;
3316 s32 ret_val = E1000_SUCCESS;
3336 ret_val = phy->ops.read_reg(hw,
3339 if (ret_val)
3340 return ret_val;
3343 ret_val = phy->ops.write_reg(hw,
3346 if (ret_val)
3347 return ret_val;
3349 ret_val = phy->ops.read_reg(hw,
3352 if (ret_val)
3353 return ret_val;
3356 ret_val = phy->ops.write_reg(hw,
3359 if (ret_val)
3360 return ret_val;
3378 ret_val = phy->ops.read_reg(hw,
3381 if (ret_val)
3382 return ret_val;
3385 ret_val = phy->ops.write_reg(hw,
3390 return ret_val;
3409 s32 ret_val;
3422 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3424 if (ret_val)
3425 return ret_val;
3434 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3437 if (ret_val)
3438 return ret_val;
3467 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3469 if (ret_val)
3470 return ret_val;
3478 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3481 if (ret_val)
3482 return ret_val;
3509 s32 ret_val = E1000_SUCCESS;
3520 ret_val = -E1000_ERR_NVM;
3526 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3527 if (ret_val != E1000_SUCCESS) {
3535 ret_val = E1000_SUCCESS;
3544 ret_val =
3548 if (ret_val)
3559 ret_val =
3563 if (ret_val)
3581 if (ret_val)
3582 DEBUGOUT1("NVM read error: %d\n", ret_val);
3584 return ret_val;
3602 s32 ret_val = E1000_SUCCESS;
3611 ret_val = -E1000_ERR_NVM;
3617 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3618 if (ret_val != E1000_SUCCESS) {
3626 ret_val = E1000_SUCCESS;
3631 ret_val = e1000_read_flash_word_ich8lan(hw,
3634 if (ret_val)
3643 if (ret_val)
3644 DEBUGOUT1("NVM read error: %d\n", ret_val);
3646 return ret_val;
3659 s32 ret_val = -E1000_ERR_NVM;
3700 ret_val = E1000_SUCCESS;
3711 ret_val = E1000_SUCCESS;
3716 if (ret_val == E1000_SUCCESS) {
3732 return ret_val;
3834 s32 ret_val;
3843 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3845 if (ret_val)
3846 return ret_val;
3869 s32 ret_val = -E1000_ERR_NVM;
3882 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3883 if (ret_val != E1000_SUCCESS)
3893 ret_val = e1000_flash_cycle_ich8lan(hw,
3901 if (ret_val == E1000_SUCCESS) {
3926 return ret_val;
3943 s32 ret_val = -E1000_ERR_NVM;
3957 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3958 if (ret_val != E1000_SUCCESS)
3975 ret_val = e1000_flash_cycle_ich8lan(hw,
3983 if (ret_val == E1000_SUCCESS) {
4004 return ret_val;
4059 s32 ret_val;
4064 ret_val = e1000_update_nvm_checksum_generic(hw);
4065 if (ret_val)
4077 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4078 if (ret_val != E1000_SUCCESS) {
4086 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4087 if (ret_val)
4092 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4093 if (ret_val)
4101 ret_val = e1000_read_flash_dword_ich8lan(hw,
4114 if (ret_val)
4134 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4136 if (ret_val)
4143 if (ret_val) {
4157 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4159 if (ret_val)
4163 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4165 if (ret_val)
4177 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4179 if (ret_val)
4183 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4185 if (ret_val)
4200 if (!ret_val) {
4206 if (ret_val)
4207 DEBUGOUT1("NVM update error: %d\n", ret_val);
4209 return ret_val;
4228 s32 ret_val;
4233 ret_val = e1000_update_nvm_checksum_generic(hw);
4234 if (ret_val)
4246 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4247 if (ret_val != E1000_SUCCESS) {
4255 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4256 if (ret_val)
4261 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4262 if (ret_val)
4269 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4272 if (ret_val)
4291 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4294 if (ret_val)
4298 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4301 if (ret_val)
4308 if (ret_val) {
4319 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4320 if (ret_val)
4324 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4326 if (ret_val)
4336 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4338 if (ret_val)
4353 if (!ret_val) {
4359 if (ret_val)
4360 DEBUGOUT1("NVM update error: %d\n", ret_val);
4362 return ret_val;
4375 s32 ret_val;
4399 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4400 if (ret_val)
4401 return ret_val;
4405 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4406 if (ret_val)
4407 return ret_val;
4408 ret_val = hw->nvm.ops.update(hw);
4409 if (ret_val)
4410 return ret_val;
4432 s32 ret_val;
4451 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4452 if (ret_val != E1000_SUCCESS)
4490 ret_val =
4493 if (ret_val == E1000_SUCCESS)
4511 return ret_val;
4528 s32 ret_val;
4542 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4543 if (ret_val != E1000_SUCCESS)
4578 ret_val = e1000_flash_cycle_ich8lan(hw,
4581 if (ret_val == E1000_SUCCESS)
4600 return ret_val;
4633 s32 ret_val;
4641 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4643 if (!ret_val)
4644 return ret_val;
4648 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4649 if (ret_val == E1000_SUCCESS)
4670 s32 ret_val;
4675 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4676 if (!ret_val)
4677 return ret_val;
4682 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4683 if (ret_val == E1000_SUCCESS)
4708 s32 ret_val;
4759 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4760 if (ret_val)
4761 return ret_val;
4791 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4792 if (ret_val == E1000_SUCCESS)
4805 return ret_val;
4823 s32 ret_val;
4827 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4828 if (ret_val) {
4830 return ret_val;
4855 s32 ret_val;
4863 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4864 if (ret_val)
4865 return ret_val;
4923 s32 ret_val;
4927 ret_val = e1000_get_bus_info_pcie_generic(hw);
4937 return ret_val;
4952 s32 ret_val;
4959 ret_val = e1000_disable_pcie_master_generic(hw);
4960 if (ret_val)
4986 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4987 if (ret_val)
4988 return ret_val;
5012 ret_val = e1000_acquire_swflag_ich8lan(hw);
5026 if (!ret_val)
5030 ret_val = hw->phy.ops.get_cfg_done(hw);
5031 if (ret_val)
5032 return ret_val;
5034 ret_val = e1000_post_phy_reset_ich8lan(hw);
5035 if (ret_val)
5036 return ret_val;
5072 s32 ret_val;
5080 ret_val = mac->ops.id_led_init(hw);
5082 if (ret_val)
5101 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5102 if (ret_val)
5103 return ret_val;
5107 ret_val = mac->ops.setup_link(hw);
5143 return ret_val;
5240 s32 ret_val;
5263 ret_val = hw->mac.ops.setup_physical_interface(hw);
5264 if (ret_val)
5265 return ret_val;
5274 ret_val = hw->phy.ops.write_reg(hw,
5277 if (ret_val)
5278 return ret_val;
5295 s32 ret_val;
5309 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5311 if (ret_val)
5312 return ret_val;
5313 ret_val = e1000_read_kmrn_reg_generic(hw,
5316 if (ret_val)
5317 return ret_val;
5319 ret_val = e1000_write_kmrn_reg_generic(hw,
5322 if (ret_val)
5323 return ret_val;
5327 ret_val = e1000_copper_link_setup_igp(hw);
5328 if (ret_val)
5329 return ret_val;
5333 ret_val = e1000_copper_link_setup_m88(hw);
5334 if (ret_val)
5335 return ret_val;
5339 ret_val = e1000_copper_link_setup_82577(hw);
5340 if (ret_val)
5341 return ret_val;
5344 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5346 if (ret_val)
5347 return ret_val;
5363 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5365 if (ret_val)
5366 return ret_val;
5386 s32 ret_val;
5395 ret_val = e1000_copper_link_setup_82577(hw);
5396 if (ret_val)
5397 return ret_val;
5415 s32 ret_val;
5419 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5420 if (ret_val)
5421 return ret_val;
5426 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5429 return ret_val;
5451 s32 ret_val;
5464 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5470 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5471 if (ret_val)
5472 return ret_val;
5474 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5475 if (ret_val)
5476 return ret_val;
5592 s32 ret_val;
5601 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5603 if (ret_val)
5606 ret_val = e1000_write_kmrn_reg_generic(hw,
5609 if (ret_val)
5634 s32 ret_val;
5655 ret_val = hw->phy.ops.acquire(hw);
5656 if (ret_val)
5662 ret_val =
5666 if (ret_val)
5744 ret_val = hw->phy.ops.acquire(hw);
5745 if (ret_val)
5766 s32 ret_val;
5772 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5773 if (ret_val) {
5774 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5775 return ret_val;
5786 ret_val = hw->phy.ops.acquire(hw);
5787 if (ret_val) {
5789 return ret_val;
5802 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5804 if (ret_val)
5813 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5815 if (ret_val)
5820 if (ret_val)
5821 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5823 return ret_val;
5988 s32 ret_val = E1000_SUCCESS;
6000 ret_val = e1000_get_auto_rd_done_generic(hw);
6001 if (ret_val) {
6007 ret_val = E1000_SUCCESS;
6028 ret_val = -E1000_ERR_CONFIG;
6032 return ret_val;
6062 s32 ret_val;
6087 ret_val = hw->phy.ops.acquire(hw);
6088 if (ret_val)
6090 ret_val = hw->phy.ops.set_page(hw,
6092 if (ret_val)