Cross Reference: /illumos-gate/usr/src/uts/common/io/e1000api/e1000

Lines Matching defs:nvm
634 	struct e1000_nvm_info *nvm = &hw->nvm;
642 	nvm->type = e1000_nvm_flash_sw;
651 		nvm->flash_base_addr = 0;
655 		nvm->flash_bank_size = nvm_size / 2;
657 		nvm->flash_bank_size /= sizeof(u16);
677 		nvm->flash_base_addr = sector_base_addr
683 		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
685 		nvm->flash_bank_size /= 2;
687 		nvm->flash_bank_size /= sizeof(u16);
690 	nvm->word_size = E1000_SHADOW_RAM_WORDS;
693 	for (i = 0; i < nvm->word_size; i++) {
702 	nvm->ops.acquire	= e1000_acquire_nvm_ich8lan;
703 	nvm->ops.release	= e1000_release_nvm_ich8lan;
705 		nvm->ops.read	= e1000_read_nvm_spt;
706 		nvm->ops.update	= e1000_update_nvm_checksum_spt;
708 		nvm->ops.read	= e1000_read_nvm_ich8lan;
709 		nvm->ops.update	= e1000_update_nvm_checksum_ich8lan;
711 	nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
712 	nvm->ops.validate	= e1000_validate_nvm_checksum_ich8lan;
713 	nvm->ops.write		= e1000_write_nvm_ich8lan;
1823 	hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
2354 		ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2359 		ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
3404 	struct e1000_nvm_info *nvm = &hw->nvm;
3405 	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3415 		bank1_offset = nvm->flash_bank_size;
3506 	struct e1000_nvm_info *nvm = &hw->nvm;
3517 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3519 		DEBUGOUT("nvm parameter(s) out of bounds\n");
3524 	nvm->ops.acquire(hw);
3532 	act_offset = (bank) ? nvm->flash_bank_size : 0;
3578 	nvm->ops.release(hw);
3599 	struct e1000_nvm_info *nvm = &hw->nvm;
3608 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3610 		DEBUGOUT("nvm parameter(s) out of bounds\n");
3615 	nvm->ops.acquire(hw);
3623 	act_offset = (bank) ? nvm->flash_bank_size : 0;
3640 	nvm->ops.release(hw);
3877 			     hw->nvm.flash_base_addr);
3952 			     hw->nvm.flash_base_addr);
4019 	struct e1000_nvm_info *nvm = &hw->nvm;
4025 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
4027 		DEBUGOUT("nvm parameter(s) out of bounds\n");
4031 	nvm->ops.acquire(hw);
4038 	nvm->ops.release(hw);
4056 	struct e1000_nvm_info *nvm = &hw->nvm;
4068 	if (nvm->type != e1000_nvm_flash_sw)
4071 	nvm->ops.acquire(hw);
4084 		new_bank_offset = nvm->flash_bank_size;
4090 		old_bank_offset = nvm->flash_bank_size;
4195 	nvm->ops.release(hw);
4201 		nvm->ops.reload(hw);
4225 	struct e1000_nvm_info *nvm = &hw->nvm;
4237 	if (nvm->type != e1000_nvm_flash_sw)
4240 	nvm->ops.acquire(hw);
4253 		new_bank_offset = nvm->flash_bank_size;
4259 		old_bank_offset = nvm->flash_bank_size;
4348 	nvm->ops.release(hw);
4354 		nvm->ops.reload(hw);
4399 	ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4405 		ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4408 		ret_val = hw->nvm.ops.update(hw);
4446 			     hw->nvm.flash_base_addr);
4538 			     hw->nvm.flash_base_addr);
4702 	struct e1000_nvm_info *nvm = &hw->nvm;
4707 	u32 flash_bank_size = nvm->flash_bank_size * 2;
4751 	flash_linear_addr = hw->nvm.flash_base_addr;
4827 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4863 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);