Lines Matching defs:hw
74 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
86 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
87 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
91 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
93 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
95 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
97 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
99 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
100 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
102 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
104 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
105 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
106 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
109 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
110 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
111 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
113 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
114 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
115 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
116 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
117 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
118 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
119 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
120 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
121 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
122 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
123 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
124 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
125 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
127 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
129 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
131 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
133 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
135 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
137 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
139 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
141 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
142 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
143 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
144 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
145 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
146 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
147 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
192 * @hw: pointer to the HW structure
198 * Assumes the sw/fw/hw semaphore is already acquired.
200 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
209 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
214 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
223 if (hw->phy.id) {
224 if (hw->phy.id == phy_id)
227 hw->phy.id = phy_id;
228 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
235 if (hw->mac.type < e1000_pch_lpt) {
236 hw->phy.ops.release(hw);
237 ret_val = e1000_set_mdio_slow_mode_hv(hw);
239 ret_val = e1000_get_phy_id(hw);
240 hw->phy.ops.acquire(hw);
246 if ((hw->mac.type == e1000_pch_lpt) ||
247 (hw->mac.type == e1000_pch_spt)) {
249 if (!(E1000_READ_REG(hw, E1000_FWSM) &
252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
259 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
268 * @hw: pointer to the HW structure
273 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
280 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
283 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
286 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
289 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
290 E1000_WRITE_FLUSH(hw);
293 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
294 E1000_WRITE_FLUSH(hw);
296 if (hw->mac.type < e1000_pch_lpt) {
303 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
312 * @hw: pointer to the HW structure
317 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
319 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
327 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
332 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
333 e1000_disable_ulp_lpt_lp(hw, TRUE);
335 ret_val = hw->phy.ops.acquire(hw);
345 switch (hw->mac.type) {
348 if (e1000_phy_is_accessible_pchlan(hw))
354 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
356 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
366 if (e1000_phy_is_accessible_pchlan(hw))
371 if ((hw->mac.type == e1000_pchlan) &&
375 if (hw->phy.ops.check_reset_block(hw)) {
382 e1000_toggle_lanphypc_pch_lpt(hw);
383 if (hw->mac.type >= e1000_pch_lpt) {
384 if (e1000_phy_is_accessible_pchlan(hw))
390 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
392 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
394 if (e1000_phy_is_accessible_pchlan(hw))
404 hw->phy.ops.release(hw);
408 if (hw->phy.ops.check_reset_block(hw)) {
418 ret_val = e1000_phy_hw_reset_generic(hw);
428 ret_val = hw->phy.ops.check_reset_block(hw);
435 if ((hw->mac.type == e1000_pch2lan) &&
438 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
446 * @hw: pointer to the HW structure
450 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
452 struct e1000_phy_info *phy = &hw->phy;
480 ret_val = e1000_init_phy_workarounds_pchlan(hw);
485 switch (hw->mac.type) {
487 ret_val = e1000_get_phy_id(hw);
499 ret_val = e1000_set_mdio_slow_mode_hv(hw);
502 ret_val = e1000_get_phy_id(hw);
536 * @hw: pointer to the HW structure
540 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
542 struct e1000_phy_info *phy = &hw->phy;
567 ret_val = e1000_determine_phy_address(hw);
571 ret_val = e1000_determine_phy_address(hw);
582 ret_val = e1000_get_phy_id(hw);
627 * @hw: pointer to the HW structure
632 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
634 struct e1000_nvm_info *nvm = &hw->nvm;
635 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
644 if (hw->mac.type == e1000_pch_spt) {
653 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
659 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
662 if (!hw->flash_address) {
667 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
704 if (hw->mac.type == e1000_pch_spt) {
720 * @hw: pointer to the HW structure
725 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
727 struct e1000_mac_info *mac = &hw->mac;
732 hw->phy.media_type = e1000_media_type_copper;
757 /* hw initialization */
828 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
835 * @hw: pointer to the HW structure
842 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
849 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
854 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
857 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
865 * @hw: pointer to the HW structure
871 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
875 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
880 * @hw: pointer to the HW structure
886 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
890 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
895 * @hw: pointer to the HW structure
907 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
909 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
915 switch (hw->phy.type) {
930 ret_val = hw->phy.ops.acquire(hw);
934 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
944 ret_val = e1000_read_emi_reg_locked(hw, lpa,
950 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
961 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
974 if (hw->phy.type == e1000_phy_82579) {
975 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
981 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
986 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
990 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
992 hw->phy.ops.release(hw);
999 * @hw: pointer to the HW structure
1008 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1010 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1011 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1016 ret_val = hw->phy.ops.acquire(hw);
1021 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1027 e1000_write_kmrn_reg_locked(hw,
1036 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1040 e1000_write_kmrn_reg_locked(hw,
1044 hw->phy.ops.release(hw);
1049 if ((hw->phy.revision > 5) || !link ||
1054 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1076 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1081 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1100 * @hw: pointer to the HW structure
1117 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1134 if (!hw->mac.max_frame_size) {
1139 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1146 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1157 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1175 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1176 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1198 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1201 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1203 E1000_WRITE_REG(hw, E1000_SVT, reg);
1206 reg = E1000_READ_REG(hw, E1000_SVCR);
1213 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1220 * @hw: pointer to the HW structure
1225 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1241 svcr = E1000_READ_REG(hw, E1000_SVCR);
1244 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1251 * @hw: pointer to the HW structure
1259 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1266 if ((hw->mac.type < e1000_pch_lpt) ||
1267 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1268 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1269 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1270 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1271 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1274 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1276 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1278 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1287 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1290 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1299 (E1000_READ_REG(hw, E1000_FEXT) &
1304 ret_val = hw->phy.ops.acquire(hw);
1309 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1313 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1316 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1318 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1323 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1324 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1332 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1342 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1348 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1360 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1363 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1365 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1369 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1371 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1372 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1373 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1380 hw->phy.ops.release(hw);
1385 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1392 * @hw: pointer to the HW structure
1405 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1412 if ((hw->mac.type < e1000_pch_lpt) ||
1413 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1414 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1415 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1416 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1417 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1420 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1423 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1426 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1430 while (E1000_READ_REG(hw, E1000_FWSM) &
1442 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1444 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1447 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1449 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1455 ret_val = hw->phy.ops.acquire(hw);
1461 e1000_toggle_lanphypc_pch_lpt(hw);
1464 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1469 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1471 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1475 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1481 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1484 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1486 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1491 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1495 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1498 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1509 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1513 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1516 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1518 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1521 hw->phy.ops.release(hw);
1523 hw->phy.ops.reset(hw);
1530 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1537 * @hw: pointer to the HW structure
1543 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1545 struct e1000_mac_info *mac = &hw->mac;
1565 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1569 if (hw->mac.type == e1000_pchlan) {
1570 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1579 if (((hw->mac.type == e1000_pch2lan) ||
1580 (hw->mac.type == e1000_pch_lpt) ||
1581 (hw->mac.type == e1000_pch_spt)) && link) {
1584 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1585 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1592 } else if (hw->mac.type == e1000_pch_spt &&
1602 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1604 ret_val = hw->phy.ops.acquire(hw);
1608 if (hw->mac.type == e1000_pch2lan)
1612 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1614 if (hw->mac.type == e1000_pch_lpt ||
1615 hw->mac.type == e1000_pch_spt) {
1618 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1625 hw->phy.ops.write_reg_locked(hw,
1630 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1635 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1639 hw->phy.ops.release(hw);
1644 if (hw->mac.type == e1000_pch_spt) {
1649 ret_val = hw->phy.ops.acquire(hw);
1653 ret_val = hw->phy.ops.read_reg_locked(hw,
1657 hw->phy.ops.release(hw);
1666 hw->phy.ops.write_reg_locked(hw,
1669 hw->phy.ops.release(hw);
1673 ret_val = hw->phy.ops.acquire(hw);
1677 ret_val = hw->phy.ops.write_reg_locked(hw,
1680 hw->phy.ops.release(hw);
1693 if ((hw->mac.type == e1000_pch_lpt) ||
1694 (hw->mac.type == e1000_pch_spt)) {
1697 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1700 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1704 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1705 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1706 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1707 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1708 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1712 if ((hw->mac.type == e1000_pch_lpt) ||
1713 (hw->mac.type == e1000_pch_spt)) {
1718 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1724 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1727 if (hw->mac.type == e1000_pch_spt) {
1728 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1729 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1732 (hw->dev_spec.ich8lan.disable_k1_off == FALSE))
1737 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1745 switch (hw->mac.type) {
1747 ret_val = e1000_k1_workaround_lv(hw);
1752 if (hw->phy.type == e1000_phy_82578) {
1753 ret_val = e1000_link_stall_workaround_hv(hw);
1763 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1766 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1770 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1779 e1000_check_downshift_generic(hw);
1782 if (hw->phy.type > e1000_phy_82579) {
1783 ret_val = e1000_set_eee_pchlan(hw);
1798 mac->ops.config_collision_dist(hw);
1805 ret_val = e1000_config_fc_after_link_up_generic(hw);
1814 * @hw: pointer to the HW structure
1818 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1822 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1823 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1824 switch (hw->mac.type) {
1828 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1834 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1843 * @hw: pointer to the HW structure
1847 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1851 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1858 * @hw: pointer to the HW structure
1862 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1866 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1873 * @hw: pointer to the HW structure
1878 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1885 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1888 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1905 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1908 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1918 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1920 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1927 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1934 * @hw: pointer to the HW structure
1939 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1945 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1949 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1951 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1954 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1961 * @hw: pointer to the HW structure
1967 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1973 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1982 * @hw: pointer to the HW structure
1988 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1994 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2002 * @hw: pointer to the HW structure
2011 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
2031 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2032 E1000_WRITE_FLUSH(hw);
2033 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2034 E1000_WRITE_FLUSH(hw);
2041 if (index < (u32) (hw->mac.rar_entry_count)) {
2044 ret_val = e1000_acquire_swflag_ich8lan(hw);
2048 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
2049 E1000_WRITE_FLUSH(hw);
2050 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
2051 E1000_WRITE_FLUSH(hw);
2053 e1000_release_swflag_ich8lan(hw);
2056 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2057 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2061 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2071 * @hw: pointer to the HW structure
2080 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2100 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2101 E1000_WRITE_FLUSH(hw);
2102 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2103 E1000_WRITE_FLUSH(hw);
2110 if (index < hw->mac.rar_entry_count) {
2111 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2122 ret_val = e1000_acquire_swflag_ich8lan(hw);
2127 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2129 E1000_WRITE_FLUSH(hw);
2130 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2132 E1000_WRITE_FLUSH(hw);
2134 e1000_release_swflag_ich8lan(hw);
2137 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2138 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2150 * @hw: pointer to the HW structure
2157 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2167 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2169 ret_val = hw->phy.ops.acquire(hw);
2173 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2177 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2178 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2179 (u16)(hw->mac.mta_shadow[i] &
2181 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2182 (u16)((hw->mac.mta_shadow[i] >> 16) &
2186 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2189 hw->phy.ops.release(hw);
2194 * @hw: pointer to the HW structure
2200 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2209 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2222 * @hw: pointer to the HW structure
2227 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2230 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2237 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2245 if (hw->phy.type == e1000_phy_i217) {
2258 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2263 * @hw: pointer to the HW structure
2268 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2270 struct e1000_phy_info *phy = &hw->phy;
2283 switch (hw->mac.type) {
2288 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2289 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2304 ret_val = hw->phy.ops.acquire(hw);
2308 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2315 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2316 if ((hw->mac.type < e1000_pch2lan) &&
2320 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2329 if (((hw->mac.type == e1000_pchlan) &&
2331 (hw->mac.type > e1000_pchlan)) {
2337 ret_val = e1000_write_smbus_addr(hw);
2341 data = E1000_READ_REG(hw, E1000_LEDCTL);
2342 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2354 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2359 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2373 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2380 hw->phy.ops.release(hw);
2386 * @hw: pointer to the HW structure
2394 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2398 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2402 if (hw->mac.type != e1000_pchlan)
2406 ret_val = hw->phy.ops.acquire(hw);
2412 if (hw->phy.type == e1000_phy_82578) {
2413 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2428 if (hw->phy.type == e1000_phy_82577) {
2429 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2445 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2452 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2458 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2461 hw->phy.ops.release(hw);
2468 * @hw: pointer to the HW structure
2476 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2486 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2496 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2502 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2503 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2507 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2509 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2510 E1000_WRITE_FLUSH(hw);
2512 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2513 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2514 E1000_WRITE_FLUSH(hw);
2522 * @hw: pointer to the HW structure
2529 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2537 if (hw->mac.type < e1000_pchlan)
2540 ret_val = hw->phy.ops.acquire(hw);
2544 if (hw->mac.type == e1000_pchlan) {
2545 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2550 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2554 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2556 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2579 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2580 !hw->phy.ops.check_reset_block(hw))
2583 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2586 hw->phy.ops.release(hw);
2594 * @hw: pointer to the HW structure
2596 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2603 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2609 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2618 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2625 if (hw->mac.type != e1000_pchlan)
2629 if (hw->phy.type == e1000_phy_82577) {
2630 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2635 if (((hw->phy.type == e1000_phy_82577) &&
2636 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2637 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2639 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2644 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2650 if (hw->phy.type == e1000_phy_82578) {
2654 if (hw->phy.revision < 2) {
2655 e1000_phy_sw_reset_generic(hw);
2656 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2662 ret_val = hw->phy.ops.acquire(hw);
2666 hw->phy.addr = 1;
2667 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2668 hw->phy.ops.release(hw);
2675 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2680 ret_val = hw->phy.ops.acquire(hw);
2683 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2686 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2692 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2694 hw->phy.ops.release(hw);
2701 * @hw: pointer to the HW structure
2703 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2711 ret_val = hw->phy.ops.acquire(hw);
2714 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2719 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2720 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2721 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2723 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2726 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2727 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2729 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2734 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2737 hw->phy.ops.release(hw);
2761 * @hw: pointer to the HW structure
2764 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2773 if (hw->mac.type < e1000_pch2lan)
2777 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2778 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2787 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2791 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2794 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2802 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2807 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2810 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2813 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2815 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2817 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2819 ret_val = e1000_read_kmrn_reg_generic(hw,
2824 ret_val = e1000_write_kmrn_reg_generic(hw,
2829 ret_val = e1000_read_kmrn_reg_generic(hw,
2836 ret_val = e1000_write_kmrn_reg_generic(hw,
2843 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2846 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2849 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2851 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2854 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2857 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2860 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2863 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2864 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2870 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2872 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2874 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2876 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2878 ret_val = e1000_read_kmrn_reg_generic(hw,
2883 ret_val = e1000_write_kmrn_reg_generic(hw,
2888 ret_val = e1000_read_kmrn_reg_generic(hw,
2895 ret_val = e1000_write_kmrn_reg_generic(hw,
2902 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2904 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2907 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2909 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2912 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2915 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2918 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2921 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2922 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2929 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2937 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2943 if (hw->mac.type != e1000_pch2lan)
2947 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2951 ret_val = hw->phy.ops.acquire(hw);
2955 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2959 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2961 hw->phy.ops.release(hw);
2968 * @hw: pointer to the HW structure
2973 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2980 if (hw->mac.type != e1000_pch2lan)
2984 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2995 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
3000 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
3006 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
3009 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
3018 * @hw: pointer to the HW structure
3024 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
3030 if (hw->mac.type < e1000_pch2lan)
3033 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
3040 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
3045 * @hw: pointer to the HW structure
3050 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3058 data = E1000_READ_REG(hw, E1000_STATUS);
3071 data = E1000_READ_REG(hw, E1000_STATUS);
3073 E1000_WRITE_REG(hw, E1000_STATUS, data);
3078 * @hw: pointer to the HW structure
3080 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3087 if (hw->phy.ops.check_reset_block(hw))
3094 switch (hw->mac.type) {
3096 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3101 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3110 if (hw->mac.type >= e1000_pchlan) {
3111 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3113 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3117 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3122 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
3124 if (hw->mac.type == e1000_pch2lan) {
3126 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3129 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
3133 ret_val = hw->phy.ops.acquire(hw);
3136 ret_val = e1000_write_emi_reg_locked(hw,
3139 hw->phy.ops.release(hw);
3147 * @hw: pointer to the HW structure
3153 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3160 if ((hw->mac.type == e1000_pch2lan) &&
3161 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3162 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3164 ret_val = e1000_phy_hw_reset_generic(hw);
3168 return e1000_post_phy_reset_ich8lan(hw);
3173 * @hw: pointer to the HW structure
3179 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3182 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3188 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3197 if (!hw->phy.ops.check_reset_block(hw))
3200 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3205 * @hw: pointer to the HW structure
3216 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3218 struct e1000_phy_info *phy = &hw->phy;
3228 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3232 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3240 if (hw->mac.type == e1000_ich8lan)
3241 e1000_gig_downshift_workaround_ich8lan(hw);
3244 ret_val = phy->ops.read_reg(hw,
3250 ret_val = phy->ops.write_reg(hw,
3257 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3268 ret_val = phy->ops.read_reg(hw,
3275 ret_val = phy->ops.write_reg(hw,
3281 ret_val = phy->ops.read_reg(hw,
3288 ret_val = phy->ops.write_reg(hw,
3301 * @hw: pointer to the HW structure
3312 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3314 struct e1000_phy_info *phy = &hw->phy;
3321 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3325 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3336 ret_val = phy->ops.read_reg(hw,
3343 ret_val = phy->ops.write_reg(hw,
3349 ret_val = phy->ops.read_reg(hw,
3356 ret_val = phy->ops.write_reg(hw,
3366 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3374 if (hw->mac.type == e1000_ich8lan)
3375 e1000_gig_downshift_workaround_ich8lan(hw);
3378 ret_val = phy->ops.read_reg(hw,
3385 ret_val = phy->ops.write_reg(hw,
3395 * @hw: pointer to the HW structure
3401 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3404 struct e1000_nvm_info *nvm = &hw->nvm;
3413 switch (hw->mac.type) {
3422 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3434 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3450 eecd = E1000_READ_REG(hw, E1000_EECD);
3467 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3478 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3496 * @hw: pointer to the HW structure
3503 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3506 struct e1000_nvm_info *nvm = &hw->nvm;
3507 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3524 nvm->ops.acquire(hw);
3526 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3545 e1000_read_flash_dword_ich8lan(hw,
3560 e1000_read_flash_dword_ich8lan(hw,
3578 nvm->ops.release(hw);
3589 * @hw: pointer to the HW structure
3596 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3599 struct e1000_nvm_info *nvm = &hw->nvm;
3600 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3615 nvm->ops.acquire(hw);
3617 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3631 ret_val = e1000_read_flash_word_ich8lan(hw,
3640 nvm->ops.release(hw);
3651 * @hw: pointer to the HW structure
3656 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3663 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3671 /* Clear FCERR and DAEL in hw status by writing 1 */
3674 if (hw->mac.type == e1000_pch_spt)
3675 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3678 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3694 if (hw->mac.type == e1000_pch_spt)
3695 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3698 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3708 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3721 if (hw->mac.type == e1000_pch_spt)
3722 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3725 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3737 * @hw: pointer to the HW structure
3742 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3751 if (hw->mac.type == e1000_pch_spt)
3752 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3754 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3757 if (hw->mac.type == e1000_pch_spt)
3758 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3761 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3765 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3779 * @hw: pointer to the HW structure
3786 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3797 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3802 * @hw: pointer to the HW structure
3809 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3820 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3825 * @hw: pointer to the HW structure
3831 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3840 if (hw->mac.type == e1000_pch_spt)
3843 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3855 * @hw: pointer to the HW structure
3862 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3877 hw->nvm.flash_base_addr);
3882 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3885 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3890 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3891 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3893 ret_val = e1000_flash_cycle_ich8lan(hw,
3902 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3914 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3931 * @hw: pointer to the HW structure
3937 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3949 hw->mac.type != e1000_pch_spt)
3952 hw->nvm.flash_base_addr);
3957 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3963 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3971 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3973 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3975 ret_val = e1000_flash_cycle_ich8lan(hw,
3984 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3992 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4009 * @hw: pointer to the HW structure
4016 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
4019 struct e1000_nvm_info *nvm = &hw->nvm;
4020 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4031 nvm->ops.acquire(hw);
4038 nvm->ops.release(hw);
4045 * @hw: pointer to the HW structure
4054 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4056 struct e1000_nvm_info *nvm = &hw->nvm;
4057 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4064 ret_val = e1000_update_nvm_checksum_generic(hw);
4071 nvm->ops.acquire(hw);
4077 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4086 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4092 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4101 ret_val = e1000_read_flash_dword_ich8lan(hw,
4134 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4157 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4163 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4177 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4183 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4195 nvm->ops.release(hw);
4201 nvm->ops.reload(hw);
4214 * @hw: pointer to the HW structure
4223 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4225 struct e1000_nvm_info *nvm = &hw->nvm;
4226 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4233 ret_val = e1000_update_nvm_checksum_generic(hw);
4240 nvm->ops.acquire(hw);
4246 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4255 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4261 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4269 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4291 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4298 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4319 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4324 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4336 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4348 nvm->ops.release(hw);
4354 nvm->ops.reload(hw);
4367 * @hw: pointer to the HW structure
4373 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4387 switch (hw->mac.type) {
4399 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4405 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4408 ret_val = hw->nvm.ops.update(hw);
4413 return e1000_validate_nvm_checksum_generic(hw);
4418 * @hw: pointer to the HW structure
4425 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4437 if (hw->mac.type == e1000_pch_spt) {
4446 hw->nvm.flash_base_addr);
4451 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4457 if (hw->mac.type == e1000_pch_spt)
4459 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4462 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4471 if (hw->mac.type == e1000_pch_spt)
4472 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4475 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4478 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4485 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4491 e1000_flash_cycle_ich8lan(hw,
4501 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4516 * @hw: pointer to the HW structure
4522 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4533 if (hw->mac.type == e1000_pch_spt) {
4538 hw->nvm.flash_base_addr);
4542 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4549 if (hw->mac.type == e1000_pch_spt)
4550 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4554 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4564 if (hw->mac.type == e1000_pch_spt)
4565 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4568 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4571 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4573 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4578 ret_val = e1000_flash_cycle_ich8lan(hw,
4589 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4605 * @hw: pointer to the HW structure
4611 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4618 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4623 * @hw: pointer to the HW structure
4630 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4641 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4648 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4660 * @hw: pointer to the HW structure
4667 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4675 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4682 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4694 * @hw: pointer to the HW structure
4700 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4702 struct e1000_nvm_info *nvm = &hw->nvm;
4714 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4716 /* Determine HW Sector size: Read BERASE bits of hw flash status
4751 flash_linear_addr = hw->nvm.flash_base_addr;
4759 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4764 * Cycle field in hw flash control
4766 if (hw->mac.type == e1000_pch_spt)
4768 E1000_READ_FLASH_REG(hw,
4772 E1000_READ_FLASH_REG16(hw,
4776 if (hw->mac.type == e1000_pch_spt)
4777 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4780 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4788 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4791 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4799 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4814 * @hw: pointer to the HW structure
4821 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4827 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4841 * @hw: pointer to the HW structure
4852 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4854 struct e1000_mac_info *mac = &hw->mac;
4863 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4867 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4915 * @hw: pointer to the HW structure
4920 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4922 struct e1000_bus_info *bus = &hw->bus;
4927 ret_val = e1000_get_bus_info_pcie_generic(hw);
4942 * @hw: pointer to the HW structure
4947 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4949 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4959 ret_val = e1000_disable_pcie_master_generic(hw);
4964 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4970 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4971 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4972 E1000_WRITE_FLUSH(hw);
4977 if (hw->mac.type == e1000_ich8lan) {
4979 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4981 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4984 if (hw->mac.type == e1000_pchlan) {
4986 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4996 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4998 if (!hw->phy.ops.check_reset_block(hw)) {
5008 if ((hw->mac.type == e1000_pch2lan) &&
5009 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
5010 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
5012 ret_val = e1000_acquire_swflag_ich8lan(hw);
5014 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
5019 if (hw->mac.type == e1000_pch2lan) {
5020 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
5023 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
5027 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
5030 ret_val = hw->phy.ops.get_cfg_done(hw);
5034 ret_val = e1000_post_phy_reset_ich8lan(hw);
5043 if (hw->mac.type == e1000_pchlan)
5044 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5046 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5047 E1000_READ_REG(hw, E1000_ICR);
5049 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5051 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5058 * @hw: pointer to the HW structure
5068 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5070 struct e1000_mac_info *mac = &hw->mac;
5077 e1000_initialize_hw_bits_ich8lan(hw);
5080 ret_val = mac->ops.id_led_init(hw);
5086 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5091 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5097 if (hw->phy.type == e1000_phy_82578) {
5098 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5100 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5101 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5107 ret_val = mac->ops.setup_link(hw);
5110 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5115 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5116 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5121 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5130 e1000_set_pcie_no_snoop_generic(hw, snoop);
5132 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5134 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5141 e1000_clear_hw_cntrs_ich8lan(hw);
5148 * @hw: pointer to the HW structure
5153 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5160 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5163 if (hw->mac.type >= e1000_pchlan)
5165 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5168 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5170 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5173 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5175 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5178 reg = E1000_READ_REG(hw, E1000_TARC(0));
5179 if (hw->mac.type == e1000_ich8lan)
5182 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5185 reg = E1000_READ_REG(hw, E1000_TARC(1));
5186 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5191 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5194 if (hw->mac.type == e1000_ich8lan) {
5195 reg = E1000_READ_REG(hw, E1000_STATUS);
5197 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5203 reg = E1000_READ_REG(hw, E1000_RFCTL);
5209 if (hw->mac.type == e1000_ich8lan)
5211 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5214 if ((hw->mac.type == e1000_pch_lpt) ||
5215 (hw->mac.type == e1000_pch_spt)) {
5216 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5218 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5220 reg = E1000_READ_REG(hw, E1000_CTRL);
5222 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5230 * @hw: pointer to the HW structure
5238 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5244 if (hw->phy.ops.check_reset_block(hw))
5251 if (hw->fc.requested_mode == e1000_fc_default)
5252 hw->fc.requested_mode = e1000_fc_full;
5257 hw->fc.current_mode = hw->fc.requested_mode;
5260 hw->fc.current_mode);
5263 ret_val = hw->mac.ops.setup_physical_interface(hw);
5267 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5268 if ((hw->phy.type == e1000_phy_82578) ||
5269 (hw->phy.type == e1000_phy_82579) ||
5270 (hw->phy.type == e1000_phy_i217) ||
5271 (hw->phy.type == e1000_phy_82577)) {
5272 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5274 ret_val = hw->phy.ops.write_reg(hw,
5276 hw->fc.pause_time);
5281 return e1000_set_fc_watermarks_generic(hw);
5286 * @hw: pointer to the HW structure
5292 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5300 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5303 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5309 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5313 ret_val = e1000_read_kmrn_reg_generic(hw,
5319 ret_val = e1000_write_kmrn_reg_generic(hw,
5325 switch (hw->phy.type) {
5327 ret_val = e1000_copper_link_setup_igp(hw);
5333 ret_val = e1000_copper_link_setup_m88(hw);
5339 ret_val = e1000_copper_link_setup_82577(hw);
5344 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5351 switch (hw->phy.mdix) {
5363 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5372 return e1000_setup_copper_link_generic(hw);
5377 * @hw: pointer to the HW structure
5383 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5390 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5393 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5395 ret_val = e1000_copper_link_setup_82577(hw);
5399 return e1000_setup_copper_link_generic(hw);
5404 * @hw: pointer to the HW structure
5412 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5419 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5423 if ((hw->mac.type == e1000_ich8lan) &&
5424 (hw->phy.type == e1000_phy_igp_3) &&
5426 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5434 * @hw: pointer to the HW structure
5447 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5449 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5464 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5470 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5474 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5483 hw->phy.ops.reset(hw);
5487 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5490 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5495 e1000_gig_downshift_workaround_ich8lan(hw);
5503 * @hw: pointer to the HW structure
5509 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5512 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5516 if (hw->mac.type != e1000_ich8lan) {
5528 * @hw: pointer to the HW structure
5536 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5544 if (hw->phy.type != e1000_phy_igp_3)
5550 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5553 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5558 if (hw->mac.type == e1000_ich8lan)
5559 e1000_gig_downshift_workaround_ich8lan(hw);
5562 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5564 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5568 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5574 reg = E1000_READ_REG(hw, E1000_CTRL);
5575 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5582 * @hw: pointer to the HW structure
5590 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5597 if ((hw->mac.type != e1000_ich8lan) ||
5598 (hw->phy.type == e1000_phy_ife))
5601 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5606 ret_val = e1000_write_kmrn_reg_generic(hw,
5612 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5618 * @hw: pointer to the HW structure
5630 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5632 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5638 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5641 if (hw->phy.type == e1000_phy_i217) {
5642 u16 phy_reg, device_id = hw->device_id;
5648 (hw->mac.type == e1000_pch_spt)) {
5649 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5651 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5655 ret_val = hw->phy.ops.acquire(hw);
5663 e1000_read_emi_reg_locked(hw,
5677 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5682 hw->phy.ops.read_reg_locked(hw,
5686 hw->phy.ops.write_reg_locked(hw,
5699 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5702 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5705 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5711 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5713 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5716 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5718 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5724 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5726 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5729 hw->phy.ops.release(hw);
5732 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5734 if (hw->mac.type == e1000_ich8lan)
5735 e1000_gig_downshift_workaround_ich8lan(hw);
5737 if (hw->mac.type >= e1000_pchlan) {
5738 e1000_oem_bits_config_ich8lan(hw, FALSE);
5741 if (hw->mac.type == e1000_pchlan)
5742 e1000_phy_hw_reset_generic(hw);
5744 ret_val = hw->phy.ops.acquire(hw);
5747 e1000_write_smbus_addr(hw);
5748 hw->phy.ops.release(hw);
5756 * @hw: pointer to the HW structure
5764 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5769 if (hw->mac.type < e1000_pch2lan)
5772 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5783 if (hw->phy.type == e1000_phy_i217) {
5786 ret_val = hw->phy.ops.acquire(hw);
5793 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5795 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5797 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5802 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5807 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5810 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5813 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5818 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5822 hw->phy.ops.release(hw);
5830 * @hw: pointer to the HW structure
5834 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5838 if (hw->phy.type == e1000_phy_ife)
5839 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5842 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5848 * @hw: pointer to the HW structure
5852 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5856 if (hw->phy.type == e1000_phy_ife)
5857 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5860 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5866 * @hw: pointer to the HW structure
5870 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5874 if (hw->phy.type == e1000_phy_ife)
5875 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5878 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5884 * @hw: pointer to the HW structure
5888 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5892 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5893 (u16)hw->mac.ledctl_mode1);
5898 * @hw: pointer to the HW structure
5902 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5906 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5907 (u16)hw->mac.ledctl_default);
5912 * @hw: pointer to the HW structure
5916 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5918 u16 data = (u16)hw->mac.ledctl_mode2;
5926 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5939 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5944 * @hw: pointer to the HW structure
5948 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5950 u16 data = (u16)hw->mac.ledctl_mode1;
5958 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5971 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5976 * @hw: pointer to the HW structure
5986 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5994 e1000_get_cfg_done_generic(hw);
5997 if (hw->mac.type >= e1000_ich10lan) {
5998 e1000_lan_init_done_ich8lan(hw);
6000 ret_val = e1000_get_auto_rd_done_generic(hw);
6012 status = E1000_READ_REG(hw, E1000_STATUS);
6014 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
6019 if (hw->mac.type <= e1000_ich9lan) {
6020 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
6021 (hw->phy.type == e1000_phy_igp_3)) {
6022 e1000_phy_init_script_igp3(hw);
6025 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
6037 * @hw: pointer to the HW structure
6042 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6045 if (!(hw->mac.ops.check_mng_mode(hw) ||
6046 hw->phy.ops.check_reset_block(hw)))
6047 e1000_power_down_phy_copper(hw);
6054 * @hw: pointer to the HW structure
6059 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6066 e1000_clear_hw_cntrs_base_generic(hw);
6068 E1000_READ_REG(hw, E1000_ALGNERRC);
6069 E1000_READ_REG(hw, E1000_RXERRC);
6070 E1000_READ_REG(hw, E1000_TNCRS);
6071 E1000_READ_REG(hw, E1000_CEXTERR);
6072 E1000_READ_REG(hw, E1000_TSCTC);
6073 E1000_READ_REG(hw, E1000_TSCTFC);
6075 E1000_READ_REG(hw, E1000_MGTPRC);
6076 E1000_READ_REG(hw, E1000_MGTPDC);
6077 E1000_READ_REG(hw, E1000_MGTPTC);
6079 E1000_READ_REG(hw, E1000_IAC);
6080 E1000_READ_REG(hw, E1000_ICRXOC);
6083 if ((hw->phy.type == e1000_phy_82578) ||
6084 (hw->phy.type == e1000_phy_82579) ||
6085 (hw->phy.type == e1000_phy_i217) ||
6086 (hw->phy.type == e1000_phy_82577)) {
6087 ret_val = hw->phy.ops.acquire(hw);
6090 ret_val = hw->phy.ops.set_page(hw,
6094 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6095 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6096 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6097 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6098 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6099 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6100 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6101 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6102 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6103 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6104 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6105 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6106 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6107 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6109 hw->phy.ops.release(hw);