Lines Matching refs:ret_val

57 	s32 ret_val;
61 ret_val = e1000_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
63 return ret_val;
93 s32 ret_val = E1000_SUCCESS;
100 ret_val = -E1000_ERR_SWFW_SYNC;
119 ret_val = -E1000_ERR_SWFW_SYNC;
129 return ret_val;
327 s32 ret_val = E1000_SUCCESS;
338 ret_val = -E1000_ERR_NVM;
352 ret_val = E1000_SUCCESS;
358 if (ret_val != E1000_SUCCESS) {
365 return ret_val;
421 s32 ret_val = E1000_SUCCESS;
428 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, &data[0]);
429 ret_val |= e1000_read_invm_word_i210(hw, (u8)offset+1,
431 ret_val |= e1000_read_invm_word_i210(hw, (u8)offset+2,
433 if (ret_val != E1000_SUCCESS)
437 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
438 if (ret_val != E1000_SUCCESS) {
440 ret_val = E1000_SUCCESS;
444 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
445 if (ret_val != E1000_SUCCESS) {
447 ret_val = E1000_SUCCESS;
451 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
452 if (ret_val != E1000_SUCCESS) {
454 ret_val = E1000_SUCCESS;
458 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
459 if (ret_val != E1000_SUCCESS) {
461 ret_val = E1000_SUCCESS;
465 ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);
466 if (ret_val != E1000_SUCCESS) {
468 ret_val = E1000_SUCCESS;
488 return ret_val;
539 s32 ret_val;
550 ret_val = e1000_read_nvm_eerd(hw, 0, 1, &nvm_data);
551 if (ret_val != E1000_SUCCESS) {
564 ret_val = e1000_read_nvm_eerd(hw, i, 1, &nvm_data);
565 if (ret_val) {
573 ret_val = e1000_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
575 if (ret_val != E1000_SUCCESS) {
583 ret_val = e1000_update_flash_i210(hw);
585 ret_val = E1000_ERR_SWFW_SYNC;
588 return ret_val;
599 bool ret_val = FALSE;
606 ret_val = TRUE;
608 return ret_val;
618 s32 ret_val;
623 ret_val = e1000_pool_flash_update_done_i210(hw);
624 if (ret_val == -E1000_ERR_NVM) {
632 ret_val = e1000_pool_flash_update_done_i210(hw);
633 if (ret_val == E1000_SUCCESS)
639 return ret_val;
649 s32 ret_val = -E1000_ERR_NVM;
657 ret_val = E1000_SUCCESS;
663 return ret_val;
674 s32 ret_val;
679 ret_val = e1000_init_nvm_params_82575(hw);
696 return ret_val;
723 s32 ret_val;
727 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
728 if (ret_val) {
745 return ret_val;
759 s32 ret_val;
763 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
764 if (ret_val)
765 return ret_val;
767 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
768 if (ret_val)
769 return ret_val;
771 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
773 if (ret_val)
774 return ret_val;
777 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
779 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
780 if (ret_val)
781 return ret_val;
784 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
785 if (ret_val)
786 return ret_val;
788 return ret_val;
828 s32 ret_val;
840 ret_val = e1000_read_invm_word_i210(hw, E1000_INVM_AUTOLOAD,
842 if (ret_val != E1000_SUCCESS)
851 ret_val = E1000_SUCCESS;
854 ret_val = -E1000_ERR_PHY;
882 return ret_val;
922 s32 ret_val;
927 ret_val = e1000_pll_workaround_i210(hw);
928 if (ret_val != E1000_SUCCESS)
929 return ret_val;
932 ret_val = e1000_init_hw_82575(hw);
933 return ret_val;