Lines Matching refs:ret_val
97 s32 ret_val;
168 ret_val = e1000_get_phy_id_82571(hw);
169 if (ret_val) {
171 return ret_val;
179 ret_val = -E1000_ERR_PHY;
183 ret_val = -E1000_ERR_PHY;
188 ret_val = -E1000_ERR_PHY;
191 ret_val = -E1000_ERR_PHY;
195 if (ret_val)
198 return ret_val;
467 s32 ret_val;
487 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
488 if (ret_val)
489 return ret_val;
493 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
494 if (ret_val)
495 return ret_val;
652 s32 ret_val;
657 ret_val = e1000_get_hw_semaphore_82573(hw);
658 if (ret_val)
660 return ret_val;
745 s32 ret_val;
749 ret_val = e1000_get_hw_semaphore_82571(hw);
750 if (ret_val)
751 return ret_val;
757 ret_val = e1000_acquire_nvm_generic(hw);
761 if (ret_val)
764 return ret_val;
796 s32 ret_val;
804 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
808 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
811 ret_val = -E1000_ERR_NVM;
815 return ret_val;
829 s32 ret_val;
834 ret_val = e1000_update_nvm_checksum_generic(hw);
835 if (ret_val)
836 return ret_val;
916 s32 ret_val = E1000_SUCCESS;
934 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
935 if (ret_val)
940 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
941 if (ret_val)
945 return ret_val;
989 s32 ret_val;
997 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
998 if (ret_val)
999 return ret_val;
1003 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1005 if (ret_val)
1006 return ret_val;
1009 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1011 if (ret_val)
1012 return ret_val;
1014 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1016 if (ret_val)
1017 return ret_val;
1020 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1028 ret_val = phy->ops.read_reg(hw,
1031 if (ret_val)
1032 return ret_val;
1035 ret_val = phy->ops.write_reg(hw,
1038 if (ret_val)
1039 return ret_val;
1041 ret_val = phy->ops.read_reg(hw,
1044 if (ret_val)
1045 return ret_val;
1048 ret_val = phy->ops.write_reg(hw,
1051 if (ret_val)
1052 return ret_val;
1068 s32 ret_val;
1075 ret_val = e1000_disable_pcie_master_generic(hw);
1076 if (ret_val)
1095 ret_val = e1000_get_hw_semaphore_82573(hw);
1099 ret_val = e1000_get_hw_semaphore_82574(hw);
1114 if (!ret_val)
1120 if (!ret_val)
1135 ret_val = e1000_get_auto_rd_done_generic(hw);
1136 if (ret_val)
1138 return ret_val;
1170 ret_val = e1000_check_alt_mac_addr_generic(hw);
1171 if (ret_val)
1172 return ret_val;
1194 s32 ret_val;
1202 ret_val = mac->ops.id_led_init(hw);
1204 if (ret_val)
1226 ret_val = mac->ops.setup_link(hw);
1261 return ret_val;
1456 s32 ret_val;
1460 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1461 if (ret_val)
1505 s32 ret_val;
1512 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1514 if (ret_val)
1517 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1519 if (ret_val)
1573 s32 ret_val;
1585 ret_val = e1000_copper_link_setup_m88(hw);
1588 ret_val = e1000_copper_link_setup_igp(hw);
1595 if (ret_val)
1596 return ret_val;
1658 s32 ret_val = E1000_SUCCESS;
1734 ret_val =
1736 if (ret_val) {
1800 return ret_val;
1813 s32 ret_val;
1817 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1818 if (ret_val) {
1820 return ret_val;
1898 s32 ret_val;
1909 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1910 if (ret_val)
1911 return ret_val;
1921 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1922 if (ret_val)
1923 return ret_val;
1927 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1928 if (ret_val)
1929 return ret_val;
1930 ret_val = nvm->ops.update(hw);
1931 if (ret_val)
1932 return ret_val;
1949 s32 ret_val;
1955 ret_val = e1000_check_alt_mac_addr_generic(hw);
1956 if (ret_val)
1957 return ret_val;