Lines Matching defs:hw
53 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
54 static void e1000_release_nvm_82571(struct e1000_hw *hw);
55 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
57 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
58 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
59 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
60 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
62 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
63 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
64 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
65 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
66 static s32 e1000_led_on_82574(struct e1000_hw *hw);
67 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
68 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
69 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
70 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
71 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
74 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
75 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
76 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
77 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
78 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
79 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
80 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
82 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
84 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
85 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
87 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
88 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
92 * @hw: pointer to the HW structure
94 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
96 struct e1000_phy_info *phy = &hw->phy;
101 if (hw->phy.media_type != e1000_media_type_copper) {
117 switch (hw->mac.type) {
146 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
168 ret_val = e1000_get_phy_id_82571(hw);
175 switch (hw->mac.type) {
203 * @hw: pointer to the HW structure
205 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
207 struct e1000_nvm_info *nvm = &hw->nvm;
208 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
230 switch (hw->mac.type) {
241 E1000_WRITE_REG(hw, E1000_EECD, eecd);
262 switch (hw->mac.type) {
284 * @hw: pointer to the HW structure
286 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
288 struct e1000_mac_info *mac = &hw->mac;
296 switch (hw->device_id) {
300 hw->phy.media_type = e1000_media_type_fiber;
311 hw->phy.media_type = e1000_media_type_internal_serdes;
319 hw->phy.media_type = e1000_media_type_copper;
343 /* hw initialization */
367 switch (hw->mac.type) {
379 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
404 switch (hw->mac.type) {
407 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
411 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
425 swsm = E1000_READ_REG(hw, E1000_SWSM);
433 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
437 hw->dev_spec._82571.smb_counter = 0;
444 * @hw: pointer to the HW structure
448 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
452 hw->mac.ops.init_params = e1000_init_mac_params_82571;
453 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
454 hw->phy.ops.init_params = e1000_init_phy_params_82571;
459 * @hw: pointer to the HW structure
464 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
466 struct e1000_phy_info *phy = &hw->phy;
472 switch (hw->mac.type) {
483 return e1000_get_phy_id(hw);
487 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
493 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
510 * @hw: pointer to the HW structure
514 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
517 s32 sw_timeout = hw->nvm.word_size + 1;
518 s32 fw_timeout = hw->nvm.word_size + 1;
530 if (hw->dev_spec._82571.smb_counter > 2)
535 swsm = E1000_READ_REG(hw, E1000_SWSM);
545 hw->dev_spec._82571.smb_counter++;
549 swsm = E1000_READ_REG(hw, E1000_SWSM);
550 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
553 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
561 e1000_put_hw_semaphore_82571(hw);
571 * @hw: pointer to the HW structure
575 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
581 swsm = E1000_READ_REG(hw, E1000_SWSM);
585 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
590 * @hw: pointer to the HW structure
595 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
602 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
605 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
606 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
617 e1000_put_hw_semaphore_82573(hw);
627 * @hw: pointer to the HW structure
632 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
638 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
640 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
645 * @hw: pointer to the HW structure
650 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
656 E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
657 ret_val = e1000_get_hw_semaphore_82573(hw);
659 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
665 * @hw: pointer to the HW structure
670 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
674 e1000_put_hw_semaphore_82573(hw);
675 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
680 * @hw: pointer to the HW structure
690 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
692 u32 data = E1000_READ_REG(hw, E1000_POEMB);
701 E1000_WRITE_REG(hw, E1000_POEMB, data);
707 * @hw: pointer to the HW structure
716 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
718 u32 data = E1000_READ_REG(hw, E1000_POEMB);
724 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
725 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
726 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
730 E1000_WRITE_REG(hw, E1000_POEMB, data);
736 * @hw: pointer to the HW structure
743 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
749 ret_val = e1000_get_hw_semaphore_82571(hw);
753 switch (hw->mac.type) {
757 ret_val = e1000_acquire_nvm_generic(hw);
762 e1000_put_hw_semaphore_82571(hw);
769 * @hw: pointer to the HW structure
773 static void e1000_release_nvm_82571(struct e1000_hw *hw)
777 e1000_release_nvm_generic(hw);
778 e1000_put_hw_semaphore_82571(hw);
783 * @hw: pointer to the HW structure
793 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
800 switch (hw->mac.type) {
804 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
808 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
820 * @hw: pointer to the HW structure
826 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
834 ret_val = e1000_update_nvm_checksum_generic(hw);
841 if (hw->nvm.type != e1000_nvm_flash_hw)
847 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
855 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
859 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
860 E1000_WRITE_FLUSH(hw);
861 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
865 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
866 E1000_WRITE_REG(hw, E1000_EECD, eecd);
870 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
882 * @hw: pointer to the HW structure
887 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
891 if (hw->nvm.type == e1000_nvm_flash_hw)
892 e1000_fix_nvm_checksum_82571(hw);
894 return e1000_validate_nvm_checksum_generic(hw);
899 * @hw: pointer to the HW structure
911 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
914 struct e1000_nvm_info *nvm = &hw->nvm;
934 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
938 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
940 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
950 * @hw: pointer to the HW structure
954 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
961 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
977 * @hw: pointer to the HW structure
986 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
988 struct e1000_phy_info *phy = &hw->phy;
997 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1003 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1009 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1014 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1020 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1028 ret_val = phy->ops.read_reg(hw,
1035 ret_val = phy->ops.write_reg(hw,
1041 ret_val = phy->ops.read_reg(hw,
1048 ret_val = phy->ops.write_reg(hw,
1061 * @hw: pointer to the HW structure
1065 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1075 ret_val = e1000_disable_pcie_master_generic(hw);
1080 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1082 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1083 tctl = E1000_READ_REG(hw, E1000_TCTL);
1085 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1086 E1000_WRITE_FLUSH(hw);
1093 switch (hw->mac.type) {
1095 ret_val = e1000_get_hw_semaphore_82573(hw);
1099 ret_val = e1000_get_hw_semaphore_82574(hw);
1105 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1108 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1111 switch (hw->mac.type) {
1113 /* Release mutex only if the hw semaphore is acquired */
1115 e1000_put_hw_semaphore_82573(hw);
1119 /* Release mutex only if the hw semaphore is acquired */
1121 e1000_put_hw_semaphore_82574(hw);
1127 if (hw->nvm.type == e1000_nvm_flash_hw) {
1129 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1131 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1132 E1000_WRITE_FLUSH(hw);
1135 ret_val = e1000_get_auto_rd_done_generic(hw);
1145 switch (hw->mac.type) {
1151 eecd = E1000_READ_REG(hw, E1000_EECD);
1153 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1165 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1166 E1000_READ_REG(hw, E1000_ICR);
1168 if (hw->mac.type == e1000_82571) {
1170 ret_val = e1000_check_alt_mac_addr_generic(hw);
1174 e1000_set_laa_state_82571(hw, TRUE);
1178 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1179 hw->mac.serdes_link_state = e1000_serdes_link_down;
1186 * @hw: pointer to the HW structure
1190 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1192 struct e1000_mac_info *mac = &hw->mac;
1199 e1000_initialize_hw_bits_82571(hw);
1202 ret_val = mac->ops.id_led_init(hw);
1209 mac->ops.clear_vfta(hw);
1216 if (e1000_get_laa_state_82571(hw))
1218 e1000_init_rx_addrs_generic(hw, rar_count);
1223 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1226 ret_val = mac->ops.setup_link(hw);
1229 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1232 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1237 e1000_enable_tx_pkt_filtering_generic(hw);
1241 reg_data = E1000_READ_REG(hw, E1000_GCR);
1243 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1246 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1250 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1259 e1000_clear_hw_cntrs_82571(hw);
1266 * @hw: pointer to the HW structure
1270 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1277 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1279 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1282 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1284 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1287 reg = E1000_READ_REG(hw, E1000_TARC(0));
1289 switch (hw->mac.type) {
1301 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1304 reg = E1000_READ_REG(hw, E1000_TARC(1));
1305 switch (hw->mac.type) {
1310 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1314 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1321 switch (hw->mac.type) {
1325 reg = E1000_READ_REG(hw, E1000_CTRL);
1327 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1334 switch (hw->mac.type) {
1338 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1341 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1347 if (hw->mac.type == e1000_82571) {
1348 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1350 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1356 if ((hw->mac.type == e1000_82571) ||
1357 (hw->mac.type == e1000_82572)) {
1358 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1360 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1366 if (hw->mac.type <= e1000_82573) {
1367 reg = E1000_READ_REG(hw, E1000_RFCTL);
1369 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1373 switch (hw->mac.type) {
1376 reg = E1000_READ_REG(hw, E1000_GCR);
1378 E1000_WRITE_REG(hw, E1000_GCR, reg);
1386 reg = E1000_READ_REG(hw, E1000_GCR2);
1388 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1399 * @hw: pointer to the HW structure
1404 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1413 switch (hw->mac.type) {
1417 if (hw->mng_cookie.vlan_id != 0) {
1424 vfta_offset = (hw->mng_cookie.vlan_id >>
1428 1 << (hw->mng_cookie.vlan_id &
1441 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1442 E1000_WRITE_FLUSH(hw);
1448 * @hw: pointer to the HW structure
1453 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1460 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1469 * @hw: pointer to the HW structure
1473 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1480 ctrl = hw->mac.ledctl_mode2;
1481 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1486 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1490 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1497 * @hw: pointer to the HW structure
1501 bool e1000_check_phy_82574(struct e1000_hw *hw)
1512 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1517 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1532 * @hw: pointer to the HW structure
1540 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1548 switch (hw->mac.type) {
1552 if (hw->fc.requested_mode == e1000_fc_default)
1553 hw->fc.requested_mode = e1000_fc_full;
1559 return e1000_setup_link_generic(hw);
1564 * @hw: pointer to the HW structure
1570 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1577 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1580 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1582 switch (hw->phy.type) {
1585 ret_val = e1000_copper_link_setup_m88(hw);
1588 ret_val = e1000_copper_link_setup_igp(hw);
1598 return e1000_setup_copper_link_generic(hw);
1603 * @hw: pointer to the HW structure
1608 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1612 switch (hw->mac.type) {
1621 E1000_WRITE_REG(hw, E1000_SCTL,
1628 return e1000_setup_fiber_serdes_link_generic(hw);
1633 * @hw: pointer to the HW structure
1650 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1652 struct e1000_mac_info *mac = &hw->mac;
1662 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1663 status = E1000_READ_REG(hw, E1000_STATUS);
1664 E1000_READ_REG(hw, E1000_RXCW);
1667 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1694 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1695 E1000_WRITE_REG(hw, E1000_CTRL,
1728 E1000_WRITE_REG(hw, E1000_TXCW,
1731 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1735 e1000_config_fc_after_link_up_generic(hw);
1753 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1754 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1774 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1789 txcw = E1000_READ_REG(hw, E1000_TXCW);
1791 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1805 * @hw: pointer to the HW structure
1811 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1817 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1823 switch (hw->mac.type) {
1842 * @hw: pointer to the HW structure
1846 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1850 if (hw->mac.type != e1000_82571)
1853 return hw->dev_spec._82571.laa_is_present;
1858 * @hw: pointer to the HW structure
1863 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1867 if (hw->mac.type != e1000_82571)
1870 hw->dev_spec._82571.laa_is_present = state;
1880 hw->mac.ops.rar_set(hw, hw->mac.addr,
1881 hw->mac.rar_entry_count - 1);
1887 * @hw: pointer to the HW structure
1895 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1897 struct e1000_nvm_info *nvm = &hw->nvm;
1909 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1921 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1927 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1930 ret_val = nvm->ops.update(hw);
1942 * @hw: pointer to the HW structure
1944 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1948 if (hw->mac.type == e1000_82571) {
1955 ret_val = e1000_check_alt_mac_addr_generic(hw);
1960 return e1000_read_mac_addr_generic(hw);
1965 * @hw: pointer to the HW structure
1970 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1972 struct e1000_phy_info *phy = &hw->phy;
1973 struct e1000_mac_info *mac = &hw->mac;
1979 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1980 e1000_power_down_phy_copper(hw);
1987 * @hw: pointer to the HW structure
1991 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1995 e1000_clear_hw_cntrs_base_generic(hw);
1997 E1000_READ_REG(hw, E1000_PRC64);
1998 E1000_READ_REG(hw, E1000_PRC127);
1999 E1000_READ_REG(hw, E1000_PRC255);
2000 E1000_READ_REG(hw, E1000_PRC511);
2001 E1000_READ_REG(hw, E1000_PRC1023);
2002 E1000_READ_REG(hw, E1000_PRC1522);
2003 E1000_READ_REG(hw, E1000_PTC64);
2004 E1000_READ_REG(hw, E1000_PTC127);
2005 E1000_READ_REG(hw, E1000_PTC255);
2006 E1000_READ_REG(hw, E1000_PTC511);
2007 E1000_READ_REG(hw, E1000_PTC1023);
2008 E1000_READ_REG(hw, E1000_PTC1522);
2010 E1000_READ_REG(hw, E1000_ALGNERRC);
2011 E1000_READ_REG(hw, E1000_RXERRC);
2012 E1000_READ_REG(hw, E1000_TNCRS);
2013 E1000_READ_REG(hw, E1000_CEXTERR);
2014 E1000_READ_REG(hw, E1000_TSCTC);
2015 E1000_READ_REG(hw, E1000_TSCTFC);
2017 E1000_READ_REG(hw, E1000_MGTPRC);
2018 E1000_READ_REG(hw, E1000_MGTPDC);
2019 E1000_READ_REG(hw, E1000_MGTPTC);
2021 E1000_READ_REG(hw, E1000_IAC);
2022 E1000_READ_REG(hw, E1000_ICRXOC);
2024 E1000_READ_REG(hw, E1000_ICRXPTC);
2025 E1000_READ_REG(hw, E1000_ICRXATC);
2026 E1000_READ_REG(hw, E1000_ICTXPTC);
2027 E1000_READ_REG(hw, E1000_ICTXATC);
2028 E1000_READ_REG(hw, E1000_ICTXQEC);
2029 E1000_READ_REG(hw, E1000_ICTXQMTC);
2030 E1000_READ_REG(hw, E1000_ICRXDMTC);