Cross Reference: /illumos-gate/usr/src/uts/common/io/e1000api/e1000

Lines Matching refs:ops
98 	phy->ops.check_polarity	= e1000_check_polarity_igp;
99 	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
100 	phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
101 	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
102 	phy->ops.get_info	= e1000_get_phy_info_igp;
103 	phy->ops.read_reg	= e1000_read_phy_reg_igp;
104 	phy->ops.reset		= e1000_phy_hw_reset_82541;
105 	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
106 	phy->ops.write_reg	= e1000_write_phy_reg_igp;
107 	phy->ops.power_up	= e1000_power_up_phy_copper;
108 	phy->ops.power_down	= e1000_power_down_phy_copper_82541;
167 		nvm->ops.acquire	= e1000_acquire_nvm_generic;
168 		nvm->ops.read		= e1000_read_nvm_spi;
169 		nvm->ops.release	= e1000_release_nvm_generic;
170 		nvm->ops.update		= e1000_update_nvm_checksum_generic;
171 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
172 		nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
173 		nvm->ops.write		= e1000_write_nvm_spi;
182 		ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
202 		nvm->ops.acquire	= e1000_acquire_nvm_generic;
203 		nvm->ops.read		= e1000_read_nvm_microwire;
204 		nvm->ops.release	= e1000_release_nvm_generic;
205 		nvm->ops.update		= e1000_update_nvm_checksum_generic;
206 		nvm->ops.valid_led_default = e1000_valid_led_default_generic;
207 		nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
208 		nvm->ops.write		= e1000_write_nvm_microwire;
237 	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
239 	mac->ops.set_lan_id = e1000_set_lan_id_single_port;
241 	mac->ops.reset_hw = e1000_reset_hw_82541;
243 	mac->ops.init_hw = e1000_init_hw_82541;
245 	mac->ops.setup_link = e1000_setup_link_generic;
247 	mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
249 	mac->ops.check_for_link = e1000_check_for_link_82541;
251 	mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
253 	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
255 	mac->ops.write_vfta = e1000_write_vfta_generic;
257 	mac->ops.clear_vfta = e1000_clear_vfta_generic;
259 	mac->ops.read_mac_addr = e1000_read_mac_addr_82541;
261 	mac->ops.id_led_init = e1000_id_led_init_generic;
263 	mac->ops.setup_led = e1000_setup_led_82541;
265 	mac->ops.cleanup_led = e1000_cleanup_led_82541;
267 	mac->ops.led_on = e1000_led_on_generic;
268 	mac->ops.led_off = e1000_led_off_generic;
270 	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
285 	hw->mac.ops.init_params = e1000_init_mac_params_82541;
286 	hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
287 	hw->phy.ops.init_params = e1000_init_phy_params_82541;
384 	ret_val = mac->ops.id_led_init(hw);
391 	ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
398 	mac->ops.clear_vfta(hw);
417 	ret_val = mac->ops.setup_link(hw);
466 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
473 		ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
641 	mac->ops.config_collision_dist(hw);
686 		ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
697 		ret_val = phy->ops.get_cable_length(hw);
705 				ret_val = phy->ops.read_reg(hw,
713 				ret_val = phy->ops.write_reg(hw,
729 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
735 			ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,
744 				ret_val = phy->ops.write_reg(hw,
762 			ret_val = phy->ops.read_reg(hw, 0x2F5B,
768 			ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
774 			ret_val = phy->ops.write_reg(hw, 0x0000,
779 				ret_val = phy->ops.read_reg(hw,
788 				ret_val = phy->ops.write_reg(hw,
795 			ret_val = phy->ops.write_reg(hw, 0x0000,
803 			ret_val = phy->ops.write_reg(hw, 0x2F5B,
820 		ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
825 		ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
831 		ret_val = phy->ops.write_reg(hw, 0x0000,
836 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,
841 		ret_val = phy->ops.write_reg(hw, 0x0000,
849 		ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
888 		ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
963 	ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
969 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
980 			ret_val = phy->ops.read_reg(hw,
987 			ret_val = phy->ops.write_reg(hw,
993 			ret_val = phy->ops.read_reg(hw,
1000 			ret_val = phy->ops.write_reg(hw,
1010 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1015 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1021 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1043 	ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
1048 	ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1074 	ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1111 	ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1114 	hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1118 	hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1125 		hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1127 		hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1129 		hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1131 		hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1133 		hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1135 		hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1137 		hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1139 		hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1141 		hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1145 		hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1151 	hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1156 	hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1162 		hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1166 			hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS,
1183 			hw->phy.ops.write_reg(hw,
1186 			hw->phy.ops.write_reg(hw,
1289 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);