Cross Reference: /illumos-gate/usr/src/uts/common/io/e1000api/e1000

Lines Matching defs:phy
87 	struct e1000_phy_info *phy = &hw->phy;
92 	phy->addr		= 1;
93 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
94 	phy->reset_delay_us	= 10000;
95 	phy->type		= e1000_phy_igp;
98 	phy->ops.check_polarity	= e1000_check_polarity_igp;
99 	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
100 	phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
101 	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
102 	phy->ops.get_info	= e1000_get_phy_info_igp;
103 	phy->ops.read_reg	= e1000_read_phy_reg_igp;
104 	phy->ops.reset		= e1000_phy_hw_reset_82541;
105 	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
106 	phy->ops.write_reg	= e1000_write_phy_reg_igp;
107 	phy->ops.power_up	= e1000_power_up_phy_copper;
108 	phy->ops.power_down	= e1000_power_down_phy_copper_82541;
114 	/* Verify phy id */
115 	if (phy->id != IGP01E1000_I_PHY_ID) {
226 	hw->phy.media_type = e1000_media_type_copper;
287 	hw->phy.ops.init_params = e1000_init_phy_params_82541;
391 	ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
447 	struct e1000_phy_info *phy = &hw->phy;
457 	if (!phy->speed_downgraded)
466 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
473 		ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
535 	struct e1000_phy_info *phy = &hw->phy;
548 	/* Earlier revs of the IGP phy require us to force MDI. */
551 		phy->mdix = 1;
671 	struct e1000_phy_info *phy = &hw->phy;
697 		ret_val = phy->ops.get_cable_length(hw);
702 		    phy->min_cable_length >= 50) {
705 				ret_val = phy->ops.read_reg(hw,
713 				ret_val = phy->ops.write_reg(hw,
723 		    (phy->min_cable_length >= 50)) {
729 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
735 			ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,
744 				ret_val = phy->ops.write_reg(hw,
762 			ret_val = phy->ops.read_reg(hw, 0x2F5B,
768 			ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
774 			ret_val = phy->ops.write_reg(hw, 0x0000,
779 				ret_val = phy->ops.read_reg(hw,
788 				ret_val = phy->ops.write_reg(hw,
795 			ret_val = phy->ops.write_reg(hw, 0x0000,
803 			ret_val = phy->ops.write_reg(hw, 0x2F5B,
820 		ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
825 		ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
831 		ret_val = phy->ops.write_reg(hw, 0x0000,
836 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,
841 		ret_val = phy->ops.write_reg(hw, 0x0000,
849 		ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
874 	struct e1000_phy_info *phy = &hw->phy;
888 		ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
917 	phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
922 	phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
925 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
947 	struct e1000_phy_info *phy = &hw->phy;
963 	ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
969 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
979 		if (phy->smart_speed == e1000_smart_speed_on) {
980 			ret_val = phy->ops.read_reg(hw,
987 			ret_val = phy->ops.write_reg(hw,
992 		} else if (phy->smart_speed == e1000_smart_speed_off) {
993 			ret_val = phy->ops.read_reg(hw,
1000 			ret_val = phy->ops.write_reg(hw,
1006 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1007 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1008 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1010 		ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1015 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1021 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1043 	ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
1048 	ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1074 	ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1104 	/* Delay after phy reset to enable NVM configuration to load */
1111 	ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1114 	hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1118 	hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1125 		hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1127 		hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1129 		hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1131 		hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1133 		hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1135 		hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1137 		hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1139 		hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1141 		hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1145 		hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1151 	hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1156 	hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1162 		hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1166 			hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS,
1183 			hw->phy.ops.write_reg(hw,
1186 			hw->phy.ops.write_reg(hw,
1210 	if (hw->phy.type != e1000_phy_igp) {