Lines Matching defs:hw
48 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
49 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
50 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
51 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
52 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
53 static s32 e1000_init_hw_82540(struct e1000_hw *hw);
54 static s32 e1000_reset_hw_82540(struct e1000_hw *hw);
55 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
56 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
57 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
58 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
59 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
60 static s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);
64 * @hw: pointer to the HW structure
66 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
68 struct e1000_phy_info *phy = &hw->phy;
89 ret_val = e1000_get_phy_id(hw);
94 switch (hw->mac.type) {
115 * @hw: pointer to the HW structure
117 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
119 struct e1000_nvm_info *nvm = &hw->nvm;
120 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
156 * @hw: pointer to the HW structure
158 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
160 struct e1000_mac_info *mac = &hw->mac;
166 switch (hw->device_id) {
171 hw->phy.media_type = e1000_media_type_fiber;
175 hw->phy.media_type = e1000_media_type_internal_serdes;
178 hw->phy.media_type = e1000_media_type_copper;
195 /* hw initialization */
201 (hw->phy.media_type == e1000_media_type_copper)
205 switch (hw->phy.media_type) {
222 (hw->phy.media_type == e1000_media_type_copper)
251 * @hw: pointer to the HW structure
255 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
259 hw->mac.ops.init_params = e1000_init_mac_params_82540;
260 hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
261 hw->phy.ops.init_params = e1000_init_phy_params_82540;
266 * @hw: pointer to the HW structure
270 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
278 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
280 E1000_WRITE_REG(hw, E1000_RCTL, 0);
281 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
282 E1000_WRITE_FLUSH(hw);
290 ctrl = E1000_READ_REG(hw, E1000_CTRL);
293 switch (hw->mac.type) {
296 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
304 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
312 manc = E1000_READ_REG(hw, E1000_MANC);
314 E1000_WRITE_REG(hw, E1000_MANC, manc);
316 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
317 E1000_READ_REG(hw, E1000_ICR);
324 * @hw: pointer to the HW structure
328 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
330 struct e1000_mac_info *mac = &hw->mac;
338 ret_val = mac->ops.id_led_init(hw);
347 E1000_WRITE_REG(hw, E1000_VET, 0);
349 mac->ops.clear_vfta(hw);
352 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
357 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
366 E1000_WRITE_FLUSH(hw);
370 e1000_pcix_mmrbc_workaround_generic(hw);
373 ret_val = mac->ops.setup_link(hw);
375 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
378 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
386 e1000_clear_hw_cntrs_82540(hw);
388 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
389 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
390 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
396 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
404 * @hw: pointer to the HW structure
411 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
419 ctrl = E1000_READ_REG(hw, E1000_CTRL);
422 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
424 ret_val = e1000_set_phy_mode_82540(hw);
428 if (hw->mac.type == e1000_82545_rev_3 ||
429 hw->mac.type == e1000_82546_rev_3) {
430 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
435 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
441 ret_val = e1000_copper_link_setup_m88(hw);
445 ret_val = e1000_setup_copper_link_generic(hw);
453 * @hw: pointer to the HW structure
460 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
462 struct e1000_mac_info *mac = &hw->mac;
470 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
475 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
480 ret_val = e1000_set_vco_speed_82540(hw);
487 ret_val = e1000_setup_fiber_serdes_link_generic(hw);
495 * @hw: pointer to the HW structure
499 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
506 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
513 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
525 * @hw: pointer to the HW structure
529 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
539 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
544 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
548 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
553 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
559 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
563 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
568 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
572 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
581 * @hw: pointer to the HW structure
588 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
595 if (hw->mac.type != e1000_82545_rev_3)
598 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
605 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
611 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
626 * @hw: pointer to the HW structure
631 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
634 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
635 e1000_power_down_phy_copper(hw);
642 * @hw: pointer to the HW structure
646 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
650 e1000_clear_hw_cntrs_base_generic(hw);
652 E1000_READ_REG(hw, E1000_PRC64);
653 E1000_READ_REG(hw, E1000_PRC127);
654 E1000_READ_REG(hw, E1000_PRC255);
655 E1000_READ_REG(hw, E1000_PRC511);
656 E1000_READ_REG(hw, E1000_PRC1023);
657 E1000_READ_REG(hw, E1000_PRC1522);
658 E1000_READ_REG(hw, E1000_PTC64);
659 E1000_READ_REG(hw, E1000_PTC127);
660 E1000_READ_REG(hw, E1000_PTC255);
661 E1000_READ_REG(hw, E1000_PTC511);
662 E1000_READ_REG(hw, E1000_PTC1023);
663 E1000_READ_REG(hw, E1000_PTC1522);
665 E1000_READ_REG(hw, E1000_ALGNERRC);
666 E1000_READ_REG(hw, E1000_RXERRC);
667 E1000_READ_REG(hw, E1000_TNCRS);
668 E1000_READ_REG(hw, E1000_CEXTERR);
669 E1000_READ_REG(hw, E1000_TSCTC);
670 E1000_READ_REG(hw, E1000_TSCTFC);
672 E1000_READ_REG(hw, E1000_MGTPRC);
673 E1000_READ_REG(hw, E1000_MGTPDC);
674 E1000_READ_REG(hw, E1000_MGTPTC);
679 * @hw: pointer to the HW structure
691 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
700 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
705 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
706 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
710 if (hw->bus.func == E1000_FUNC_1)
711 hw->mac.perm_addr[5] ^= 1;
714 hw->mac.addr[i] = hw->mac.perm_addr[i];