Lines Matching refs:ret_val
92 s32 ret_val;
127 ret_val = e1000_get_phy_id(hw);
133 return ret_val;
364 s32 ret_val;
368 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
369 if (ret_val)
370 return ret_val;
372 ret_val = e1000_acquire_nvm_generic(hw);
374 if (ret_val)
377 return ret_val;
476 s32 ret_val;
482 ret_val = e1000_acquire_phy_80003es2lan(hw);
483 if (ret_val)
484 return ret_val;
497 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
498 if (ret_val) {
500 return ret_val;
511 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
520 ret_val = e1000_read_phy_reg_mdic(hw,
526 ret_val = e1000_read_phy_reg_mdic(hw,
533 return ret_val;
547 s32 ret_val;
553 ret_val = e1000_acquire_phy_80003es2lan(hw);
554 if (ret_val)
555 return ret_val;
568 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
569 if (ret_val) {
571 return ret_val;
582 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
591 ret_val = e1000_write_phy_reg_mdic(hw,
597 ret_val = e1000_write_phy_reg_mdic(hw,
604 return ret_val;
664 s32 ret_val;
676 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
677 if (ret_val)
678 return ret_val;
681 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
682 if (ret_val)
683 return ret_val;
687 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
688 if (ret_val)
689 return ret_val;
696 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
697 if (ret_val)
698 return ret_val;
705 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
707 if (ret_val)
708 return ret_val;
714 ret_val = e1000_phy_reset_dsp_generic(hw);
715 if (ret_val)
716 return ret_val;
720 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
722 if (ret_val)
723 return ret_val;
726 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
728 if (ret_val)
729 return ret_val;
744 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
747 return ret_val;
760 s32 ret_val;
768 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
769 if (ret_val)
770 return ret_val;
796 s32 ret_val;
801 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
805 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
810 return ret_val;
822 s32 ret_val;
830 ret_val = e1000_disable_pcie_master_generic(hw);
831 if (ret_val)
845 ret_val = e1000_acquire_phy_80003es2lan(hw);
846 if (ret_val)
847 return ret_val;
854 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
856 if (!ret_val) {
858 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
861 if (ret_val)
866 ret_val = e1000_get_auto_rd_done_generic(hw);
867 if (ret_val)
869 return ret_val;
888 s32 ret_val;
897 ret_val = mac->ops.id_led_init(hw);
899 if (ret_val)
915 ret_val = mac->ops.setup_link(hw);
916 if (ret_val)
917 return ret_val;
920 ret_val =
923 if (!ret_val) {
925 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
928 if (ret_val)
969 ret_val =
972 if (!ret_val) {
985 return ret_val;
1044 s32 ret_val;
1050 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1051 if (ret_val)
1052 return ret_val;
1058 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1059 if (ret_val)
1060 return ret_val;
1069 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1070 if (ret_val)
1071 return ret_val;
1098 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1099 if (ret_val)
1100 return ret_val;
1103 ret_val = hw->phy.ops.commit(hw);
1104 if (ret_val) {
1106 return ret_val;
1113 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1114 if (ret_val)
1115 return ret_val;
1118 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1119 if (ret_val)
1120 return ret_val;
1122 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1123 if (ret_val)
1124 return ret_val;
1126 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1127 if (ret_val)
1128 return ret_val;
1131 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1132 if (ret_val)
1133 return ret_val;
1139 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1140 if (ret_val)
1141 return ret_val;
1150 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1152 if (ret_val)
1153 return ret_val;
1155 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1157 if (ret_val)
1158 return ret_val;
1161 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1163 if (ret_val)
1164 return ret_val;
1170 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1171 if (ret_val)
1172 return ret_val;
1175 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1176 if (ret_val)
1177 return ret_val;
1192 s32 ret_val;
1206 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1208 if (ret_val)
1209 return ret_val;
1210 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1212 if (ret_val)
1213 return ret_val;
1215 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1217 if (ret_val)
1218 return ret_val;
1219 ret_val =
1223 if (ret_val)
1224 return ret_val;
1226 ret_val =
1230 if (ret_val)
1231 return ret_val;
1233 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1234 if (ret_val)
1235 return ret_val;
1250 s32 ret_val = E1000_SUCCESS;
1257 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1259 if (ret_val)
1260 return ret_val;
1263 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1265 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1268 return ret_val;
1281 s32 ret_val;
1289 ret_val =
1293 if (ret_val)
1294 return ret_val;
1303 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1305 if (ret_val)
1306 return ret_val;
1308 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1310 if (ret_val)
1311 return ret_val;
1332 s32 ret_val;
1340 ret_val =
1344 if (ret_val)
1345 return ret_val;
1354 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1356 if (ret_val)
1357 return ret_val;
1359 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1361 if (ret_val)
1362 return ret_val;
1385 s32 ret_val;
1389 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1390 if (ret_val)
1391 return ret_val;
1405 return ret_val;
1422 s32 ret_val;
1426 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1427 if (ret_val)
1428 return ret_val;
1439 return ret_val;
1448 s32 ret_val;
1456 ret_val = e1000_check_alt_mac_addr_generic(hw);
1457 if (ret_val)
1458 return ret_val;