Lines Matching defs:reg_data
887 u32 reg_data;
934 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
935 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
937 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
940 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
941 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
943 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
946 reg_data = E1000_READ_REG(hw, E1000_TCTL);
947 reg_data |= E1000_TCTL_RTLC;
948 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
951 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
952 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
953 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
954 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
957 reg_data = E1000_READ_REG(hw, E1000_TIPG);
958 reg_data &= ~E1000_TIPG_IPGT_MASK;
959 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
960 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
962 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
963 reg_data &= ~0x00100000;
964 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
1193 u16 reg_data;
1211 ®_data);
1214 reg_data |= 0x3F;
1216 reg_data);
1222 ®_data);
1225 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1229 reg_data);
1284 u16 reg_data, reg_data2;
1288 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1292 reg_data);
1304 ®_data);
1313 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1316 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1318 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1320 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1333 u16 reg_data, reg_data2;
1339 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1343 reg_data);
1355 ®_data);
1364 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1366 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1368 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);