Lines Matching defs:phy
91 struct e1000_phy_info *phy = &hw->phy;
96 if (hw->phy.media_type != e1000_media_type_copper) {
97 phy->type = e1000_phy_none;
100 phy->ops.power_up = e1000_power_up_phy_copper;
101 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
104 phy->addr = 1;
105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
106 phy->reset_delay_us = 100;
107 phy->type = e1000_phy_gg82563;
109 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
110 phy->ops.check_polarity = e1000_check_polarity_m88;
111 phy->ops.check_reset_block = e1000_check_reset_block_generic;
112 phy->ops.commit = e1000_phy_sw_reset_generic;
113 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
114 phy->ops.get_info = e1000_get_phy_info_m88;
115 phy->ops.release = e1000_release_phy_80003es2lan;
116 phy->ops.reset = e1000_phy_hw_reset_generic;
117 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
119 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
120 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
121 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
122 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
124 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
129 /* Verify phy id */
130 if (phy->id != GG82563_E_PHY_ID)
205 hw->phy.media_type = e1000_media_type_internal_serdes;
211 hw->phy.media_type = e1000_media_type_copper;
268 /* set lan id for port to determine which phy lock to use */
286 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
629 * This is a function pointer entry point called by the phy module.
660 * function pointer entry point called by the phy module.
670 if (!(hw->phy.ops.read_reg))
676 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
681 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
687 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
693 /* Reset the phy to commit changes. */
696 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
702 if (hw->phy.autoneg_wait_to_complete) {
703 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
726 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
731 /* Resetting the phy means we need to verify the TX_CLK corresponds
744 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
755 * This is a function pointer entry point called by the phy module.
759 struct e1000_phy_info *phy = &hw->phy;
765 if (!(hw->phy.ops.read_reg))
768 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
777 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
778 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
780 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
800 if (hw->phy.media_type == e1000_media_type_copper) {
803 hw->phy.ops.cfg_on_link_up(hw);
1013 if (hw->phy.media_type != e1000_media_type_copper)
1043 struct e1000_phy_info *phy = &hw->phy;
1050 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1058 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1069 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1075 switch (phy->mdix) {
1095 if (phy->disable_polarity_correction)
1098 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1103 ret_val = hw->phy.ops.commit(hw);
1126 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1131 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1139 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1150 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1155 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1161 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1170 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1175 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1204 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1256 if (hw->phy.media_type == e1000_media_type_copper) {
1303 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1308 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1320 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1354 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1359 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1368 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1474 hw->phy.ops.check_reset_block(hw)))