Lines Matching defs:pi
80 static int alloc_iq_fl(struct port_info *pi, struct sge_iq *iq,
82 static int free_iq_fl(struct port_info *pi, struct sge_iq *iq,
87 static int alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx,
89 static int free_rxq(struct port_info *pi, struct sge_rxq *rxq);
91 static int alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq,
93 static int free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq);
96 static int eth_eq_alloc(struct adapter *sc, struct port_info *pi,
99 static int ofld_eq_alloc(struct adapter *sc, struct port_info *pi,
102 static int alloc_eq(struct adapter *sc, struct port_info *pi,
105 static int alloc_wrq(struct adapter *sc, struct port_info *pi,
108 static int alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx);
109 static int free_txq(struct port_info *pi, struct sge_txq *txq);
143 static int write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, mblk_t *m,
145 static inline void write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq,
155 static kstat_t *setup_port_config_kstats(struct port_info *pi);
156 static kstat_t *setup_port_info_kstats(struct port_info *pi);
157 static kstat_t *setup_rxq_kstats(struct port_info *pi, struct sge_rxq *rxq,
161 static kstat_t *setup_txq_kstats(struct port_info *pi, struct sge_txq *txq,
346 first_vector(struct port_info *pi)
348 struct adapter *sc = pi->adapter;
357 if (i == pi->port_id)
384 port_intr_iq(struct port_info *pi, int idx)
386 struct adapter *sc = pi->adapter;
395 idx %= pi->nrxq + pi->nofldrxq;
397 if (idx >= pi->nrxq) {
398 idx -= pi->nrxq;
399 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq;
401 iq = &s->rxq[pi->first_rxq + idx].iq;
404 idx %= max(pi->nrxq, pi->nofldrxq);
406 if (pi->nrxq >= pi->nofldrxq)
407 iq = &s->rxq[pi->first_rxq + idx].iq;
409 iq = &s->ofld_rxq[pi->first_ofld_rxq + idx].iq;
418 idx %= pi->nrxq;
419 iq = &s->rxq[pi->first_rxq + idx].iq;
426 t4_setup_port_queues(struct port_info *pi)
436 struct adapter *sc = pi->adapter;
439 pi->ksp_config = setup_port_config_kstats(pi);
440 pi->ksp_info = setup_port_info_kstats(pi);
443 intr_idx = first_vector(pi);
451 for_each_rxq(pi, i, rxq) {
453 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, p->qsize_rxq,
460 (sc->intr_count > 1 && pi->nrxq >= pi->nofldrxq))
466 rc = alloc_rxq(pi, rxq, intr_idx, i);
475 for_each_ofld_rxq(pi, i, ofld_rxq) {
477 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx,
483 (sc->intr_count > 1 && pi->nofldrxq > pi->nrxq)) {
485 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx);
499 for_each_rxq(pi, i, rxq) {
503 intr_idx = port_intr_iq(pi, j)->abs_id;
505 rc = alloc_rxq(pi, rxq, intr_idx, i);
512 for_each_ofld_rxq(pi, i, ofld_rxq) {
516 intr_idx = port_intr_iq(pi, j)->abs_id;
517 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx);
527 for_each_txq(pi, i, txq) {
530 iqid = port_intr_iq(pi, j)->cntxt_id;
531 init_eq(&txq->eq, EQ_ETH, p->qsize_txq, pi->tx_chan, iqid);
532 rc = alloc_txq(pi, txq, i);
538 for_each_ofld_txq(pi, i, ofld_txq) {
541 iqid = port_intr_iq(pi, j)->cntxt_id;
542 init_eq(&ofld_txq->eq, EQ_OFLD, p->qsize_txq, pi->tx_chan,
544 rc = alloc_wrq(sc, pi, ofld_txq, i);
553 ctrlq = &sc->sge.ctrlq[pi->port_id];
554 iqid = port_intr_iq(pi, 0)->cntxt_id;
555 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid);
556 rc = alloc_wrq(sc, pi, ctrlq, 0);
560 (void) t4_teardown_port_queues(pi);
569 t4_teardown_port_queues(struct port_info *pi)
574 struct adapter *sc = pi->adapter;
580 if (pi->ksp_config != NULL) {
581 kstat_delete(pi->ksp_config);
582 pi->ksp_config = NULL;
584 if (pi->ksp_info != NULL) {
585 kstat_delete(pi->ksp_info);
586 pi->ksp_info = NULL;
589 (void) free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
591 for_each_txq(pi, i, txq) {
592 (void) free_txq(pi, txq);
596 for_each_ofld_txq(pi, i, ofld_txq) {
600 for_each_ofld_rxq(pi, i, ofld_rxq) {
602 (void) free_ofld_rxq(pi, ofld_rxq);
606 for_each_rxq(pi, i, rxq) {
608 (void) free_rxq(pi, rxq);
615 for_each_rxq(pi, i, rxq) {
617 (void) free_rxq(pi, rxq);
621 for_each_ofld_rxq(pi, i, ofld_rxq) {
623 (void) free_ofld_rxq(pi, ofld_rxq);
929 t4_eth_tx(struct port_info *pi, struct sge_txq *txq, mblk_t *frame)
931 struct adapter *sc = pi->adapter;
979 write_ulp_cpl_sgl(pi, txq, &txpkts, &txinfo);
996 rc = write_txpkt_wr(pi, txq, frame, &txinfo);
1098 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
1133 V_FW_IQ_CMD_VIID(pi->viid) |
1135 c.iqdroprss_to_iqesize = cpu_to_be16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
1229 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
1235 dip = pi ? pi->dip : sc->dip;
1330 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int i)
1334 rxq->port = pi;
1335 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, 1 << pi->tx_chan);
1339 rxq->ksp = setup_rxq_kstats(pi, rxq, i);
1345 free_rxq(struct port_info *pi, struct sge_rxq *rxq)
1354 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl);
1363 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq,
1368 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
1369 1 << pi->tx_chan);
1377 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq)
1381 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl);
1435 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
1447 c.viid_pkd = BE_32(V_FW_EQ_ETH_CMD_VIID(pi->viid));
1460 cxgb_printf(pi->dip, CE_WARN,
1478 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
1503 cxgb_printf(pi->dip, CE_WARN,
1521 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
1546 rc = eth_eq_alloc(sc, pi, eq);
1551 rc = ofld_eq_alloc(sc, pi, eq);
1619 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq,
1624 rc = alloc_eq(sc, pi, &wrq->eq);
1654 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx)
1657 struct adapter *sc = pi->adapter;
1660 rc = alloc_eq(sc, pi, eq);
1664 txq->port = pi;
1695 txq->ksp = setup_txq_kstats(pi, txq, idx);
1701 free_txq(struct port_info *pi, struct sge_txq *txq)
1704 struct adapter *sc = pi->adapter;
2561 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, mblk_t *m,
2647 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf));
2699 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq,
2752 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf));
3093 setup_port_config_kstats(struct port_info *pi)
3098 dev_info_t *pdip = ddi_get_parent(pi->dip);
3099 uint8_t *ma = &pi->hw_addr[0];
3104 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), "config",
3107 cxgb_printf(pi->dip, CE_WARN, "failed to initialize kstats.");
3121 KS_U_SET(idx, pi->port_id);
3122 KS_U_SET(nrxq, pi->nrxq);
3123 KS_U_SET(ntxq, pi->ntxq);
3124 KS_U_SET(first_rxq, pi->first_rxq);
3125 KS_U_SET(first_txq, pi->first_txq);
3134 ksp->ks_private = (void *)pi;
3141 setup_port_info_kstats(struct port_info *pi)
3149 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), "info",
3152 cxgb_printf(pi->dip, CE_WARN, "failed to initialize kstats.");
3172 ksp->ks_private = (void *)pi;
3183 struct port_info *pi = ksp->ks_private;
3191 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
3193 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
3195 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
3197 else if (pi->mod_type > 0 && pi->mod_type < ARRAY_SIZE(mod_str))
3198 KS_C_SET(transceiver, "%s", mod_str[pi->mod_type]);
3200 KS_C_SET(transceiver, "type %d", pi->mod_type);
3202 #define GET_STAT(name) t4_read_reg64(pi->adapter, \
3203 PORT_REG(pi->port_id, A_MPS_PORT_STAT_##name##_L))
3204 #define GET_STAT_COM(name) t4_read_reg64(pi->adapter, \
3207 bgmap = G_NUMPORTS(t4_read_reg(pi->adapter, A_MPS_CMN_CTL));
3209 bgmap = (pi->port_id == 0) ? 0xf : 0;
3211 bgmap = (pi->port_id < 2) ? (3 << (2 * pi->port_id)) : 0;
3248 setup_rxq_kstats(struct port_info *pi, struct sge_rxq *rxq, int idx)
3258 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), str, "rxq",
3261 cxgb_printf(pi->dip, CE_WARN,
3318 setup_txq_kstats(struct port_info *pi, struct sge_txq *txq, int idx)
3328 ksp = kstat_create(T4_PORT_NAME, ddi_get_instance(pi->dip), str, "txq",
3331 cxgb_printf(pi->dip, CE_WARN,