Lines Matching defs:adap
92 * @adap: the adapter
103 t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
108 t4_write_reg(adap, addr_reg, start_idx);
109 *vals++ = t4_read_reg(adap, data_reg);
116 * @adap: the adapter
127 t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
132 t4_write_reg(adap, addr_reg, start_idx++);
133 t4_write_reg(adap, data_reg, *vals++);
141 get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, u32 mbox_addr)
144 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
151 fw_asrt(struct adapter *adap, u32 mbox_addr)
155 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof (asrt) / 8, mbox_addr);
156 CH_ALERT(adap, "FW assertion at %.16s:%u, val0 %x, val1 %x",
164 * @adap: the adapter
185 t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
208 v = G_MBOWNER(t4_read_reg(adap, ctl_reg));
210 v = G_MBOWNER(t4_read_reg(adap, ctl_reg));
216 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
218 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
219 (void) t4_read_reg(adap, ctl_reg); /* flush write */
233 v = t4_read_reg(adap, ctl_reg);
238 t4_write_reg(adap, ctl_reg,
243 res = t4_read_reg64(adap, data_reg);
245 fw_asrt(adap, data_reg);
248 get_mbox_rpl(adap, rpl, size / 8, data_reg);
249 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
254 CH_ERR(adap, "command %x in mailbox %d timed out",
261 * @adap: the adapter
271 t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc)
275 if (t4_read_reg(adap, A_MC_BIST_CMD) & F_START_BIST)
277 t4_write_reg(adap, A_MC_BIST_CMD_ADDR, addr & ~0x3fU);
278 t4_write_reg(adap, A_MC_BIST_CMD_LEN, 64);
279 t4_write_reg(adap, A_MC_BIST_DATA_PATTERN, 0xc);
280 t4_write_reg(adap, A_MC_BIST_CMD, V_BIST_OPCODE(1) | F_START_BIST |
282 i = t4_wait_op_done(adap, A_MC_BIST_CMD, F_START_BIST, 0, 10, 1);
289 *data++ = htonl(t4_read_reg(adap, MC_DATA(i)));
291 *ecc = t4_read_reg64(adap, MC_DATA(16));
298 * @adap: the adapter
309 t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
314 if (t4_read_reg(adap, A_EDC_BIST_CMD + idx) & F_START_BIST)
316 t4_write_reg(adap, A_EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU);
317 t4_write_reg(adap, A_EDC_BIST_CMD_LEN + idx, 64);
318 t4_write_reg(adap, A_EDC_BIST_DATA_PATTERN + idx, 0xc);
319 t4_write_reg(adap, A_EDC_BIST_CMD + idx,
321 i = t4_wait_op_done(adap, A_EDC_BIST_CMD + idx, F_START_BIST, 0, 10, 1);
328 *data++ = htonl(t4_read_reg(adap, EDC_DATA(i)));
330 *ecc = t4_read_reg64(adap, EDC_DATA(16));
337 * @adap: the adapter
351 t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, __be32 *buf)
378 ret = t4_mc_read(adap, pos, data, NULL);
380 ret = t4_edc_read(adap, mtype, pos, data, NULL);
398 * @adap: the adapter
408 t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir)
418 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 0),
420 (void) t4_read_reg(adap, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET,
426 *data++ = t4_read_reg(adap, (MEMWIN0_BASE + i));
428 t4_write_reg(adap, (MEMWIN0_BASE + i), *data++);
435 t4_mem_win_read(struct adapter *adap, u32 addr, __be32 *data)
437 return (t4_mem_win_rw(adap, addr, data, 1));
1007 * @adap: the adapter
1014 t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
1019 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
1021 addr = t4_flash_cfg_addr(adap);
1025 CH_ERR(adap, "cfg file has no data");
1030 CH_ERR(adap, "cfg file too large, max is %u bytes",
1037 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
1048 ret = t4_write_flash(adap, addr, n, cfg_data);
1058 CH_ERR(adap, "config file download failed %d", ret);
1064 * @adap: the adapter
1071 t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
1081 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
1084 CH_ERR(adap, "FW image has no data");
1088 CH_ERR(adap, "FW image size not multiple of 512 bytes");
1092 CH_ERR(adap, "FW image size differs from size in FW header");
1096 CH_ERR(adap, "FW image too large, max is %u bytes\n",
1105 CH_ERR(adap, "corrupted firmware image, checksum %x",
1111 ret = t4_flash_erase_sectors(adap, FLASH_FW_START_SEC,
1124 ret = t4_write_flash(adap, FLASH_FW_START, SF_PAGE_SIZE, first_page);
1132 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
1137 ret = t4_write_flash(adap,
1142 CH_ERR(adap, "firmware download failed, error %d", ret);
1148 * @adap: the adapter
1157 t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
1162 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
1164 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
1170 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
1172 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
1180 * @adap: the adapter
1190 t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
1204 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
1206 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
1210 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
1212 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
1218 * @adap: the adapter
1228 t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
1236 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
1238 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
1246 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
1248 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
1252 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
1254 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
1268 * @adap: the adapter
1276 t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1281 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
1285 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
1286 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
1289 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
1296 * @adap: the adapter
1304 t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1309 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
1313 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
1314 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
1315 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
1322 t4_cim_write1(struct adapter *adap, unsigned int addr, unsigned int val)
1324 return (t4_cim_write(adap, addr, 1, &val));
1329 * @adap: the adapter
1337 t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
1340 return (t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp));
1345 * @adap: the adapter
1354 t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
1359 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
1364 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
1369 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
1377 for (i = 0; i < adap->params.cim_la_size; i++) {
1378 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
1382 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
1389 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
1396 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
1405 t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1411 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
1413 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
1415 val = t4_read_reg(adap, A_CIM_DEBUGSTS);
1425 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
1427 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
1428 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
1435 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
1439 t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
1444 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
1446 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
1451 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
1453 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
1454 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
1457 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
1462 * @adap: the adapter
1471 t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
1476 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
1478 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
1479 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
1481 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
1491 val |= adap->params.tp.la_mask;
1494 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
1495 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
1504 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
1505 cfg | adap->params.tp.la_mask);
1509 t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
1516 t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
1517 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
1518 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
1520 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
1541 t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1568 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
1573 * @adap: the adapter
1580 t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
1590 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
1957 le_intr_handler(struct adapter *adap)
1968 if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE, le_intr_info))
1969 t4_fatal_err(adap);
2111 smb_intr_handler(struct adapter *adap)
2120 if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info) != 0)
2121 t4_fatal_err(adap);
2128 ncsi_intr_handler(struct adapter *adap)
2138 if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info) != 0)
2139 t4_fatal_err(adap);
2146 xgmac_intr_handler(struct adapter *adap, int port)
2148 u32 v = t4_read_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE));
2155 CH_ALERT(adap, "XGMAC %d Tx FIFO parity error", port);
2157 CH_ALERT(adap, "XGMAC %d Rx FIFO parity error", port);
2158 t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE), v);
2159 t4_fatal_err(adap);
2166 pl_intr_handler(struct adapter *adap)
2174 if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, pl_intr_info) != 0)
2175 t4_fatal_err(adap);
2503 rd_rss_row(struct adapter *adap, int row, u32 *val)
2505 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
2506 return (t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
2535 * @adap: the adapter
2541 t4_read_rss_key(struct adapter *adap, u32 *key)
2543 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
2549 * @adap: the adapter
2558 t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
2560 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
2563 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
2728 * @adap: the adapter
2737 t4_set_filter_mode(struct adapter *adap, unsigned int mode_map)
2748 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, &mode_map, 1,
2755 * @adap: the adapter
2763 t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
2773 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
2781 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
2795 * @adap: the adapter
2801 t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
2803 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->macInErrs,
2805 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->tnlCongDrops,
2807 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->tnlTxDrops,
2809 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->ofldVlanDrops,
2811 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->tcp6InErrs,
2813 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->ofldNoNeigh,
2819 * @adap: the adapter
2825 t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st)
2827 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->proxy,
2833 * @adap: the adapter
2839 t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
2841 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->req,
2843 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->tx_err,
2849 * @adap: the adapter
2855 t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
2857 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->rqe_dfr_mod,
2863 * @adap: the adapter
2870 t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
2875 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->framesDDP,
2877 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->framesDrop,
2879 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
2886 * @adap: the adapter
2892 t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
2896 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 4,
2905 * @adap: the adapter
2912 t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
2918 t4_write_reg(adap, A_TP_MTU_TABLE,
2920 v = t4_read_reg(adap, A_TP_MTU_TABLE);
2929 * @adap: the adapter
2936 t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
2942 t4_write_reg(adap, A_TP_CCTRL_TABLE,
2944 incr[mtu][w] = (u16)t4_read_reg(adap,
2951 * @adap: the adapter
2957 t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
2962 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
2963 v = t4_read_reg(adap, A_TP_PACE_TABLE);
2964 pace_vals[i] = dack_ticks_to_usec(adap, v);
2970 * @adap: the adapter
2978 t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
2981 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
2982 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
2983 t4_write_reg(adap, A_TP_PIO_DATA, val);
3036 * @adap: the adapter
3047 t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
3064 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
3073 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
3081 * @adap: the adapter
3089 t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
3093 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
3107 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
3113 * @adap: the adapter
3120 t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
3123 unsigned int clk = adap->params.vpd.cclk * 1000;
3145 t4_write_reg(adap, A_TP_TM_PIO_ADDR,
3147 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
3152 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
3158 * @adap: the adapter
3165 t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
3170 ipg *= core_ticks_per_usec(adap);
3175 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3176 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
3181 t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
3182 (void) t4_read_reg(adap, A_TP_TM_PIO_DATA);
3188 * @adap: the adapter
3196 t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
3203 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3204 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
3212 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
3218 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3219 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
3223 *ipg = (10000 * v) / core_ticks_per_usec(adap);
3238 chan_rate(struct adapter *adap, unsigned int bytes256)
3240 u64 v = bytes256 * adap->params.vpd.cclk;
3247 * @adap: the adapter
3255 t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
3259 v = t4_read_reg(adap, A_TP_TX_TRATE);
3260 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
3261 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
3262 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
3263 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
3265 v = t4_read_reg(adap, A_TP_TX_ORATE);
3266 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
3267 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
3268 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
3269 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
3274 * @adap: the adapter
3283 t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
3291 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0);
3301 if ((t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + 4) |
3302 t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + 8) |
3303 t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + 12)) &
3308 i = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B);
3310 (t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A) & F_TFEN))
3315 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0);
3318 cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
3320 t4_write_reg(adap, A_MPS_TRC_CFG, cfg ^ F_TRCEN);
3321 (void) t4_read_reg(adap, A_MPS_TRC_CFG); /* flush */
3323 if (!(t4_read_reg(adap, A_MPS_TRC_CFG) & F_TRCFIFOEMPTY))
3336 t4_write_reg(adap, data_reg, tp->data[i]);
3337 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
3339 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
3341 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
3346 t4_write_reg(adap, A_MPS_TRC_CFG, cfg | F_TRCEN | multitrc);
3347 out: (void) t4_read_reg(adap, A_MPS_TRC_CFG); /* flush */
3353 * @adap: the adapter
3361 t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
3368 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
3369 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
3384 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
3385 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
3391 * @adap: the adapter
3398 t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
3403 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
3404 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
3405 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
3411 * @adap: the adapter
3418 t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
3423 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
3424 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
3425 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
3431 * @adap: the adapter
3439 get_mps_bg_map(struct adapter *adap, int idx)
3441 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
3452 * @adap: the adapter
3459 t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
3461 u32 bgmap = get_mps_bg_map(adap, idx);
3464 t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))
3465 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
3534 * @adap: the adapter
3540 t4_clr_port_stats(struct adapter *adap, int idx)
3543 u32 bgmap = get_mps_bg_map(adap, idx);
3547 t4_write_reg(adap, PORT_REG(idx, i), 0);
3550 t4_write_reg(adap, PORT_REG(idx, i), 0);
3553 t4_write_reg(adap,
3555 t4_write_reg(adap,
3562 * @adap: the adapter
3569 t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
3571 u32 bgmap = get_mps_bg_map(adap, idx);
3574 t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))
3575 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
3591 p->drop = t4_read_reg(adap, PORT_REG(idx,
3609 * @adap: the adapter
3616 t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr)
3619 t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO),
3622 t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI),
3625 t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), F_MAGICEN,
3631 * @adap: the adapter
3645 t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
3651 t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2),
3660 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
3661 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
3662 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
3669 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
3670 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
3671 (void) t4_read_reg(adap, EPIO_REG(OP)); /* flush */
3672 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
3676 t4_write_reg(adap, EPIO_REG(DATA0), crc);
3677 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
3678 (void) t4_read_reg(adap, EPIO_REG(OP)); /* flush */
3679 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
3684 t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), 0, F_PATEN);
3718 * @adap: the adapter
3728 t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
3742 ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c);
3750 * @adap: the adapter
3760 t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
3774 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
3779 * @adap: the adapter
3788 t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
3809 ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c);
3823 * @adap: the adapter
3832 t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
3837 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
3838 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
3841 *data++ = t4_read_reg(adap, i);
3847 * @adap: the adapter
3857 t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3884 ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c);
3936 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3975 * @adap: the adapter
3981 t4_fw_bye(struct adapter *adap, unsigned int mbox)
3988 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
3993 * @adap: the adapter
4000 t4_early_init(struct adapter *adap, unsigned int mbox)
4007 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4012 * @adap: the adapter
4019 t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
4027 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4032 * @adap: the adapter
4057 t4_fw_config_file(struct adapter *adap, unsigned int mbox, unsigned int mtype,
4079 ret = t4_wr_mbox(adap, mbox, &caps_cmd, sizeof (caps_cmd), &caps_cmd);
4097 return (t4_wr_mbox(adap, mbox, &caps_cmd, sizeof (caps_cmd), NULL));
4102 * @adap: the adapter
4111 t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
4120 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
4130 t4_set_reg_field(adap, A_SGE_CONTROL,
4157 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
4158 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
4159 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align-1) &
4161 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
4162 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align-1) &
4165 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
4172 * @adap: the adapter
4179 t4_fw_initialize(struct adapter *adap, unsigned int mbox)
4186 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4191 * @adap: the adapter
4203 t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
4222 ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c);
4231 * @adap: the adapter
4243 t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
4263 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4268 * @adap: the adapter
4288 t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
4309 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4314 * @adap: the adapter
4330 t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
4345 ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c);
4372 * @adap: the adapter
4381 t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
4395 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), &c));
4400 * @adap: the adapter
4413 t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
4439 return (t4_wr_mbox_meat(adap, mbox, &c, sizeof (c), NULL, sleep_ok));
4444 * @adap: the adapter
4465 t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
4507 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof (c), &c, sleep_ok);
4537 * @adap: the adapter
4558 t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
4577 ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c);
4588 * @adap: the adapter
4598 t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
4609 return (t4_wr_mbox_meat(adap, mbox, &c, sizeof (c), NULL, sleep_ok));
4614 * @adap: the adapter
4623 t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
4633 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4638 * @adap: the adapter
4646 t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
4656 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4661 * @adap: the adapter
4673 t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
4688 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4693 * @adap: the adapter
4705 t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4720 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4725 * @adap: the adapter
4734 t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4745 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4750 * @adap: the adapter
4759 t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4770 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4775 * @adap: the adapter
4784 t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4795 return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL));
4800 * @adap: the adapter
4806 t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4833 for_each_port(adap, i) {
4834 pi = adap2pinfo(adap, i);
4844 t4_os_link_changed(adap, i, link_ok);
4849 t4_os_portmod_changed(adap, i);
4903 wait_dev_ready(struct adapter *adap)
4907 whoami = t4_read_reg(adap, A_PL_WHOAMI);
4913 whoami = t4_read_reg(adap, A_PL_WHOAMI);
5004 adapter_t *adap = p->adapter;
5011 } while ((adap->params.portvec & (1 << j)) == 0);
5019 ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c);
5023 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
5031 t4_os_set_hw_addr(adap, p->port_id, addr);