Lines Matching defs:cpqary3p
284 cpqary3_t *cpqary3p; /* per-controller */
304 cpqary3p = ddi_get_soft_state(cpqary3_state, instance);
305 if (!cpqary3p) {
307 cpqary3_cleanup(cpqary3p, cleanstatus);
312 cpqary3p->dip = dip;
313 cpqary3p->instance = instance;
316 cpqary3_read_conf_file(dip, cpqary3p);
319 retvalue = cpqary3_update_ctlrdetails(cpqary3p, &cleanstatus);
321 cpqary3_cleanup(cpqary3p, cleanstatus);
326 if (ddi_get_iblock_cookie(dip, 0, &cpqary3p->hw_iblock_cookie) !=
328 cpqary3_cleanup(cpqary3p, cleanstatus);
333 mutex_init(&cpqary3p->hw_mutex, NULL, MUTEX_DRIVER,
334 (void *)cpqary3p->hw_iblock_cookie);
340 &cpqary3p->sw_iblock_cookie) != DDI_SUCCESS) {
341 cpqary3_cleanup(cpqary3p, cleanstatus);
346 mutex_init(&cpqary3p->sw_mutex, NULL, MUTEX_DRIVER,
347 (void *)cpqary3p->sw_iblock_cookie);
351 retvalue = cpqary3_init_ctlr_resource(cpqary3p);
353 cpqary3_cleanup(cpqary3p, cleanstatus);
361 cpqary3p->hba_tran = scsi_hba_tran_alloc(dip, SCSI_HBA_CANSLEEP);
362 if (!cpqary3p->hba_tran) {
363 cpqary3_cleanup(cpqary3p, cleanstatus);
373 cpqary3_init_hbatran(cpqary3p);
378 tmp_dma_attr.dma_attr_sgllen = cpqary3p->sg_cnt;
385 if (scsi_hba_attach_setup(dip, &tmp_dma_attr, cpqary3p->hba_tran,
387 cpqary3_cleanup(cpqary3p, cleanstatus);
410 cpqary3_cleanup(cpqary3p, cleanstatus);
416 cpqary3p->tick_tmout_id = timeout(cpqary3_tick_hdlr,
417 (caddr_t)cpqary3p, drv_usectohz(CPQARY3_TICKTMOUT_VALUE));
422 &cpqary3p->cpqary3_softintr_id, &cpqary3p->sw_iblock_cookie, NULL,
423 cpqary3_sw_isr, (caddr_t)cpqary3p) != DDI_SUCCESS) {
424 cpqary3_cleanup(cpqary3p, cleanstatus);
430 if (ddi_add_intr(dip, 0, &cpqary3p->hw_iblock_cookie, NULL,
431 cpqary3_hw_isr, (caddr_t)cpqary3p) != DDI_SUCCESS) {
432 cpqary3_cleanup(cpqary3p, cleanstatus);
438 cpqary3_intr_onoff(cpqary3p, CPQARY3_INTR_ENABLE);
439 if (cpqary3p->host_support & 0x4)
440 cpqary3_lockup_intr_onoff(cpqary3p, CPQARY3_LOCKUP_INTR_ENABLE);
449 if (cpqary3p->noe_support == 1) {
452 cpqary3_send_NOE_command(cpqary3p,
490 cpqary3_t *cpqary3p;
504 cpqary3p = (cpqary3_t *)hba_tran->tran_hba_private;
508 cpqary3_flush_cache(cpqary3p);
512 cpqary3_cleanup(cpqary3p, CPQARY3_CLEAN_ALL);
532 cpqary3_t *cpqary3p;
558 cpqary3p = (cpqary3_t *)ddi_get_soft_state(cpqary3_state, instance);
562 if (!cpqary3p) {
585 cpqary3_ioctl_ctlr_info(arg, cpqary3p, mode);
590 cpqary3_ioctl_bmic_pass(arg, cpqary3p, mode);
595 cpqary3_ioctl_scsi_pass(arg, cpqary3p, mode);
616 cpqary3_cleanup(cpqary3_t *cpqary3p, uint32_t status)
622 ASSERT(cpqary3p != NULL);
636 if (CPQARY3_SUCCESS == cpqary3_disable_NOE_command(cpqary3p)) {
637 mutex_enter(&cpqary3p->hw_mutex);
640 cv_timedwait_sig(&cpqary3p->cv_noe_wait,
641 &cpqary3p->hw_mutex,
647 mutex_exit(&cpqary3p->hw_mutex);
665 ddi_remove_intr(cpqary3p->dip, 0, cpqary3p->hw_iblock_cookie);
668 ddi_remove_softintr(cpqary3p->cpqary3_softintr_id);
670 if ((status & CPQARY3_TICK_TMOUT_REGD) && cpqary3p->tick_tmout_id) {
671 VERIFY(untimeout(cpqary3p->tick_tmout_id) >= 0);
672 cpqary3p->tick_tmout_id = NULL;
676 (void) sprintf(node_name, "cpqary3%d", cpqary3p->instance);
677 ddi_remove_minor_node(cpqary3p->dip, node_name);
681 (void) scsi_hba_detach(cpqary3p->dip);
684 scsi_hba_tran_free(cpqary3p->hba_tran);
687 mutex_enter(&cpqary3p->hw_mutex);
689 cv_destroy(&cpqary3p->cv_abort_wait);
690 cv_destroy(&cpqary3p->cv_flushcache_wait);
691 cv_destroy(&cpqary3p->cv_noe_wait);
692 cv_destroy(&cpqary3p->cv_immediate_wait);
693 cv_destroy(&cpqary3p->cv_ioctl_wait);
696 if (cpqary3p->cpqary3_tgtp[targ] == NULL)
698 MEM_SFREE(cpqary3p->cpqary3_tgtp[targ],
702 mutex_exit(&cpqary3p->hw_mutex);
704 cpqary3_memfini(cpqary3p, CPQARY3_MEMLIST_DONE |
709 mutex_destroy(&cpqary3p->sw_mutex);
712 mutex_destroy(&cpqary3p->hw_mutex);
718 if (cpqary3p->idr_handle)
719 ddi_regs_map_free(&cpqary3p->idr_handle);
720 if (cpqary3p->isr_handle)
721 ddi_regs_map_free(&cpqary3p->isr_handle);
722 if (cpqary3p->imr_handle)
723 ddi_regs_map_free(&cpqary3p->imr_handle);
724 if (cpqary3p->ipq_handle)
725 ddi_regs_map_free(&cpqary3p->ipq_handle);
726 if (cpqary3p->opq_handle)
727 ddi_regs_map_free(&cpqary3p->opq_handle);
728 if (cpqary3p->ct_handle)
729 ddi_regs_map_free(&cpqary3p->ct_handle);
734 ddi_get_instance(cpqary3p->dip));
753 cpqary3_update_ctlrdetails(cpqary3_t *cpqary3p, uint32_t *cleanstatus)
779 RETURN_FAILURE_IF_NULL(cpqary3p);
786 if (ddi_slaveonly(cpqary3p->dip) == DDI_SUCCESS)
795 if (ddi_getlongprop(DDI_DEV_T_NONE, cpqary3p->dip, DDI_PROP_DONTPASS,
799 cpqary3p->bus = PCI_REG_BUS_G(*regp);
800 cpqary3p->dev = PCI_REG_DEV_G(*regp);
801 cpqary3p->fun = PCI_REG_FUNC_G(*regp);
845 if (pci_config_setup(cpqary3p->dip, &pci_handle) != DDI_SUCCESS)
848 cpqary3p->irq = pci_config_get8(pci_handle, PCI_CONF_ILINE);
849 cpqary3p->board_id =
860 cpqary3p->bddef = cpqary3_bd_getbybid(cpqary3p->board_id);
861 if (cpqary3p->bddef == NULL) {
864 cpqary3p->board_id);
867 map_len = cpqary3p->bddef->bd_maplen;
868 (void) strcpy(cpqary3p->hba_name, cpqary3p->bddef->bd_dispname);
880 retvalue = ddi_regs_map_setup(cpqary3p->dip,
882 (caddr_t *)&cpqary3p->idr, (offset_t)I2O_IBDB_SET, map_len,
883 &cpqary3_dev_attributes, &cpqary3p->idr_handle);
896 retvalue = ddi_regs_map_setup(cpqary3p->dip,
898 (caddr_t *)&cpqary3p->odr, (offset_t)I2O_OBDB_STATUS, map_len,
899 &cpqary3_dev_attributes, &cpqary3p->odr_handle);
911 retvalue = ddi_regs_map_setup(cpqary3p->dip,
913 (caddr_t *)&cpqary3p->odr_cl, (offset_t)I2O_OBDB_CLEAR, map_len,
914 &cpqary3_dev_attributes, &cpqary3p->odr_cl_handle);
927 retvalue = ddi_regs_map_setup(cpqary3p->dip,
929 (caddr_t *)&cpqary3p->spr0, (offset_t)I2O_CTLR_INIT, map_len,
930 &cpqary3_dev_attributes, &cpqary3p->spr0_handle);
946 retvalue = ddi_regs_map_setup(cpqary3p->dip,
948 (caddr_t *)&cpqary3p->isr, (offset_t)I2O_INT_STATUS, map_len,
949 &cpqary3_dev_attributes, &cpqary3p->isr_handle);
961 retvalue = ddi_regs_map_setup(cpqary3p->dip,
963 (caddr_t *)&cpqary3p->imr, (offset_t)I2O_INT_MASK, map_len,
964 &cpqary3_dev_attributes, &cpqary3p->imr_handle);
976 retvalue = ddi_regs_map_setup(cpqary3p->dip,
978 (caddr_t *)&cpqary3p->ipq, (offset_t)I2O_IBPOST_Q, map_len,
979 &cpqary3_dev_attributes, &cpqary3p->ipq_handle);
991 retvalue = ddi_regs_map_setup(cpqary3p->dip,
992 mem_bar0, /* INDEX_PCI_BASE0, */ (caddr_t *)&cpqary3p->opq,
994 &cpqary3p->opq_handle);
1011 retvalue = ddi_regs_map_setup(cpqary3p->dip,
1026 retvalue = ddi_regs_map_setup(cpqary3p->dip,
1074 retvalue = ddi_regs_map_setup(cpqary3p->dip,
1076 (caddr_t *)&cpqary3p->ct, (offset_t)ct_memoff_val,
1077 sizeof (CfgTable_t), &cpqary3_dev_attributes, &cpqary3p->ct_handle);
1091 retvalue = ddi_regs_map_setup(cpqary3p->dip,
1093 (caddr_t *)&cpqary3p->cp,
1094 (offset_t)(ct_memoff_val + cpqary3p->ct->TransportMethodOffset),
1096 &cpqary3p->cp_handle);