Lines Matching refs:pn
190 /* pn = port number 0-9 for tri-speed, 10 for 10GbE */
192 #define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */
193 #define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */
194 #define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */
197 * pn = port number, 0-9
199 #define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */
200 #define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */
201 #define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */
202 #define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */
203 #define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */
204 #define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */
205 #define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */
206 #define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */
207 #define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */
208 #define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */
209 #define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */
210 #define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */
211 #define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */
212 #define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */
213 #define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */
214 #define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */
215 #define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */
216 #define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */
217 #define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */
218 #define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */
221 /* pn = port number, 0-a, a = 10GbE */
222 #define REG_RX_IN_BYTES(pn) CRA(0x4,pn,0x00) /* # Rx in octets */
223 #define REG_RX_SYMBOL_CARRIER(pn) CRA(0x4,pn,0x01) /* Frames w/ symbol errors */
224 #define REG_RX_PAUSE(pn) CRA(0x4,pn,0x02) /* # pause frames received */
225 #define REG_RX_UNSUP_OPCODE(pn) CRA(0x4,pn,0x03) /* # control frames with unsupported opcode */
226 #define REG_RX_OK_BYTES(pn) CRA(0x4,pn,0x04) /* # octets in good frames */
227 #define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,0x05) /* # octets in bad frames */
228 #define REG_RX_UNICAST(pn) CRA(0x4,pn,0x06) /* # good unicast frames */
229 #define REG_RX_MULTICAST(pn) CRA(0x4,pn,0x07) /* # good multicast frames */
230 #define REG_RX_BROADCAST(pn) CRA(0x4,pn,0x08) /* # good broadcast frames */
231 #define REG_CRC(pn) CRA(0x4,pn,0x09) /* # frames w/ bad CRC only */
232 #define REG_RX_ALIGNMENT(pn) CRA(0x4,pn,0x0a) /* # frames w/ alignment err */
233 #define REG_RX_UNDERSIZE(pn) CRA(0x4,pn,0x0b) /* # frames undersize */
234 #define REG_RX_FRAGMENTS(pn) CRA(0x4,pn,0x0c) /* # frames undersize w/ crc err */
235 #define REG_RX_IN_RANGE_LENGTH_ERROR(pn) CRA(0x4,pn,0x0d) /* # frames with length error */
236 #define REG_RX_OUT_OF_RANGE_ERROR(pn) CRA(0x4,pn,0x0e) /* # frames with illegal length field */
237 #define REG_RX_OVERSIZE(pn) CRA(0x4,pn,0x0f) /* # frames oversize */
238 #define REG_RX_JABBERS(pn) CRA(0x4,pn,0x10) /* # frames oversize w/ crc err */
239 #define REG_RX_SIZE_64(pn) CRA(0x4,pn,0x11) /* # frames 64 octets long */
240 #define REG_RX_SIZE_65_TO_127(pn) CRA(0x4,pn,0x12) /* # frames 65-127 octets */
241 #define REG_RX_SIZE_128_TO_255(pn) CRA(0x4,pn,0x13) /* # frames 128-255 */
242 #define REG_RX_SIZE_256_TO_511(pn) CRA(0x4,pn,0x14) /* # frames 256-511 */
243 #define REG_RX_SIZE_512_TO_1023(pn) CRA(0x4,pn,0x15) /* # frames 512-1023 */
244 #define REG_RX_SIZE_1024_TO_1518(pn) CRA(0x4,pn,0x16) /* # frames 1024-1518 */
245 #define REG_RX_SIZE_1519_TO_MAX(pn) CRA(0x4,pn,0x17) /* # frames 1519-max */
247 #define REG_TX_OUT_BYTES(pn) CRA(0x4,pn,0x18) /* # octets tx */
248 #define REG_TX_PAUSE(pn) CRA(0x4,pn,0x19) /* # pause frames sent */
249 #define REG_TX_OK_BYTES(pn) CRA(0x4,pn,0x1a) /* # octets tx OK */
250 #define REG_TX_UNICAST(pn) CRA(0x4,pn,0x1b) /* # frames unicast */
251 #define REG_TX_MULTICAST(pn) CRA(0x4,pn,0x1c) /* # frames multicast */
252 #define REG_TX_BROADCAST(pn) CRA(0x4,pn,0x1d) /* # frames broadcast */
253 #define REG_TX_MULTIPLE_COLL(pn) CRA(0x4,pn,0x1e) /* # frames tx after multiple collisions */
254 #define REG_TX_LATE_COLL(pn) CRA(0x4,pn,0x1f) /* # late collisions detected */
255 #define REG_TX_XCOLL(pn) CRA(0x4,pn,0x20) /* # frames lost, excessive collisions */
256 #define REG_TX_DEFER(pn) CRA(0x4,pn,0x21) /* # frames deferred on first tx attempt */
257 #define REG_TX_XDEFER(pn) CRA(0x4,pn,0x22) /* # frames excessively deferred */
258 #define REG_TX_CSENSE(pn) CRA(0x4,pn,0x23) /* carrier sense errors at frame end */
259 #define REG_TX_SIZE_64(pn) CRA(0x4,pn,0x24) /* # frames 64 octets long */
260 #define REG_TX_SIZE_65_TO_127(pn) CRA(0x4,pn,0x25) /* # frames 65-127 octets */
261 #define REG_TX_SIZE_128_TO_255(pn) CRA(0x4,pn,0x26) /* # frames 128-255 */
262 #define REG_TX_SIZE_256_TO_511(pn) CRA(0x4,pn,0x27) /* # frames 256-511 */
263 #define REG_TX_SIZE_512_TO_1023(pn) CRA(0x4,pn,0x28) /* # frames 512-1023 */
264 #define REG_TX_SIZE_1024_TO_1518(pn) CRA(0x4,pn,0x29) /* # frames 1024-1518 */
265 #define REG_TX_SIZE_1519_TO_MAX(pn) CRA(0x4,pn,0x2a) /* # frames 1519-max */
266 #define REG_TX_SINGLE_COLL(pn) CRA(0x4,pn,0x2b) /* # frames tx after single collision */
267 #define REG_TX_BACKOFF2(pn) CRA(0x4,pn,0x2c) /* # frames tx ok after 2 backoffs/collisions */
268 #define REG_TX_BACKOFF3(pn) CRA(0x4,pn,0x2d) /* after 3 backoffs/collisions */
269 #define REG_TX_BACKOFF4(pn) CRA(0x4,pn,0x2e) /* after 4 */
270 #define REG_TX_BACKOFF5(pn) CRA(0x4,pn,0x2f) /* after 5 */
271 #define REG_TX_BACKOFF6(pn) CRA(0x4,pn,0x30) /* after 6 */
272 #define REG_TX_BACKOFF7(pn) CRA(0x4,pn,0x31) /* after 7 */
273 #define REG_TX_BACKOFF8(pn) CRA(0x4,pn,0x32) /* after 8 */
274 #define REG_TX_BACKOFF9(pn) CRA(0x4,pn,0x33) /* after 9 */
275 #define REG_TX_BACKOFF10(pn) CRA(0x4,pn,0x34) /* after 10 */
276 #define REG_TX_BACKOFF11(pn) CRA(0x4,pn,0x35) /* after 11 */
277 #define REG_TX_BACKOFF12(pn) CRA(0x4,pn,0x36) /* after 12 */
278 #define REG_TX_BACKOFF13(pn) CRA(0x4,pn,0x37) /* after 13 */
279 #define REG_TX_BACKOFF14(pn) CRA(0x4,pn,0x38) /* after 14 */
280 #define REG_TX_BACKOFF15(pn) CRA(0x4,pn,0x39) /* after 15 */
281 #define REG_TX_UNDERRUN(pn) CRA(0x4,pn,0x3a) /* # frames dropped from underrun */
283 #define REG_RX_IPG_SHRINK(pn) CRA(0x4,pn,0x3c) /* # of IPG shrinks detected */
285 #define REG_STAT_STICKY1G(pn) CRA(0x4,pn,0x3e) /* tri-speed sticky bits */
287 #define REG_STAT_INIT(pn) CRA(0x4,pn,0x3f) /* Clear all statistics */